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Sync mode configuration sampling

Thread Summary

The user inquired about the LTM8060's SYNC pin behavior, specifically the timing of mode changes and the transition to an external sync clock. The final answer confirmed that the SYNC mode can be changed dynamically, and the device locks directly to the external clock once detected, without a gradual ramp. The transition is generally clean but may cause minor cycle-to-cycle perturbations. The RT value is linearly related to Fsw, and using 60.4 kΩ for 650 kHz is reasonable. The LTspice model does not accurately capture the exact lock-in time, which is typically within tens to a few hundred microseconds in hardware.
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Category: Datasheet/Specs
Product Number: LTM8060

The LTM8060 Sync inputs are multimode function selectors as well as external clock synchronization inputs.  When are the Sync pins sampled?  There is no description or spec of timing relative to Vin-on or to RUNn pins.  Can we assume that the mode can be changed on-the-fly?  When transitioning from any of the three modes (Burst mode, FCM, Spread-Spectrum) to external sync clock, is there a clean ramp from the RT set frequency to the sync input frequency (required to be higher than RT setting)?

I've configured the LTM8060 jig in the LTSpice examples library for 3.3V @ 6A plus 2.5V and 1.8V @ 3A each, circuit below; 

The following waveform is a zoomed-in section of channels 1,2 at the end of a 5msec run where a 1.4MHz clock had been applied at 1.5msec following startup.  The 3.3V stabilized at 600usec after startup.  The green trace is the applied 1.4MHz signal on SYNC12, the pink trace is CLKOUT12, and the grey trace is the ripple current in Rload1.  By this point of the waveform, the device had 3.5msec of SYNC clock present.

Three things are noticeable in this capture; first, the load ripple current shows that the Fsw has not locked onto the 1.4MHz and is still only a bit higher than the 1.23MHz preset prior to application of the SYNC clock. Second, the ripple is 2x the Fsw setting, meaning that the two channels are running at 180 degrees to each other.  That's not a surprise and is a good thing although there is no mention of this in the datasheet.  Third,  the two phases appear to be a bit imbalanced from each other.  They were nicely even prior to the application of the SYNC clock. 

I know that the SYNC input is not being ignored given the following trace capture showing a Rload1 ripple step disturbance at 0.5msec where SYNC12 clocking begins and CLKOUT12 starts sending (I set data storage to 1msec from start, so the clock application occurs 1.5msec from sim startup and nearly 1msec after the 3.3V output stabilized into a 6.6A load)

At this point, either the Spice model of the LTM8060 does not properly capture the chip behaviour, or there are a number of unspecified parameters regarding the SYNC function.  I'm glad that it appears that the SYNC mode can be changed on-the-fly, however, I need to know the stabilization time after a mode change, or if there are any restrictions on which mode changes are permitted while the channels are running. 

Edit Notes

Some further investigation regarding mode configuration using LTSpice
[edited by: RP555 at 10:30 PM (GMT -4) on 29 Apr 2026]
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  • Hi Rick,

    The LTspice model of the LTM8060 is intended to represent correct steady‑state behavior and overall control functionality, including external synchronization, but it does not model detailed internal timing such as exact SYNC detection or lock timing. As a result, the lock‑in time you observe in simulation should be considered indicative rather than a guaranteed silicon parameter. In hardware, synchronization typically occurs within tens to a few hundred microseconds, consistent with other sync‑capable parts, but this is not specified in the datasheet.


    I think the transition to an external sync clock is not performed as a gradual ramp from the RT frequency. Once a valid external clock is detected (and it is higher than the RT‑programmed frequency), the converter transitions to synchronizing to that clock. Regulation is maintained during the handover, but the transition is not defined as a phase‑aligned or edge‑matched event, and minor cycle‑to‑cycle perturbations can occur, as is typical when switching clock sources. ADI has evaluated synchronization behavior across modes (Burst Mode, FCM, spread‑spectrum) and loss‑of‑sync cases, but since these transitions are not guaranteed parameters, they are not explicitly specified.


    Regarding RT, the resistor programs the oscillator in a continuous, analog manner. The values shown in Table 2 are representative examples, not discrete frequency steps. Using an RT value such as 60.4 kΩ to target ~650 kHz is reasonable, with normal tolerance‑related variation.

    Charly

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  • Hi Rick,

    The LTspice model of the LTM8060 is intended to represent correct steady‑state behavior and overall control functionality, including external synchronization, but it does not model detailed internal timing such as exact SYNC detection or lock timing. As a result, the lock‑in time you observe in simulation should be considered indicative rather than a guaranteed silicon parameter. In hardware, synchronization typically occurs within tens to a few hundred microseconds, consistent with other sync‑capable parts, but this is not specified in the datasheet.


    I think the transition to an external sync clock is not performed as a gradual ramp from the RT frequency. Once a valid external clock is detected (and it is higher than the RT‑programmed frequency), the converter transitions to synchronizing to that clock. Regulation is maintained during the handover, but the transition is not defined as a phase‑aligned or edge‑matched event, and minor cycle‑to‑cycle perturbations can occur, as is typical when switching clock sources. ADI has evaluated synchronization behavior across modes (Burst Mode, FCM, spread‑spectrum) and loss‑of‑sync cases, but since these transitions are not guaranteed parameters, they are not explicitly specified.


    Regarding RT, the resistor programs the oscillator in a continuous, analog manner. The values shown in Table 2 are representative examples, not discrete frequency steps. Using an RT value such as 60.4 kΩ to target ~650 kHz is reasonable, with normal tolerance‑related variation.

    Charly

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