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LTC3350 Recommended for New Designs
The LTC3350 is a backup power controller that can charge and monitor a series stack of one to four supercapacitors. The LTC3350’s synchronous step-down...
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LTC3350 on Analog.com

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LTC3350 refuses to charge

		
	
				

			

									
					    EricChilds
					
							

            
            			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Feb 5, 2026 
				
			
			
		
    
		
		                     
				
        		
    
		    
		    		    
    
		      		            		        
    Category: Hardware
    
    		        		            		    
    Product Number:  LTC3350  
    
    		        		        		        
    Software Version: Not Applicable
    
    		    		    
    
		    		    
		    			
    
			    
    I have a circuit using LTC3350 that is showing odd behavior and wonder if anyone could help me resolve the issue?
    

    When Vin is increased from 0V to 12V the capacitors do not start charging. This behavior is consistent across all boards. The prototype worked reliably, but maybe this was a fluke?
    

    When probing the design to try to find the issue I have found that touching the PFI pin sometimes kicks the design into life and the capacitors then charge perfectly.
    

    Looking at the SW node, as I gradually increase Vin from 0V to 12V the SW node starts switching when I reach ~5V (at 500KHz as expected). However when I get past 11V it suddenly stops and the charger sits there doing nothing (see images)
    

    I've run out of things to try! I can't see anything wrong with the schematic, maybe I'm missing something?
    

    

    The design intent is as follows:
    

    1/ Vcap ~10V
    

    2/ Switches over to back-up mode when Vin falls below ~9.9V
    

    3/ Charge current limit set to 4A, but total current limited to 640mA (expectation is ~150mA load and 500mA left over for charging)
    

    4/ Backup voltage is 12V
    

    

    

     
    

     
    

    
			
    
			
									
		                             
                        

    
    
                                            
                 power management
                
                                                    
                 hardware
                
                                                    
                 Supercapacitor Chargers
                
                                                    
                 Not applicable
                
                                                    
                 LTC3350
                
                                
            
    
    
    
		
    

				
				        
        		
    
			
						
									
												
			
			
                        
                                    
                        
                                                                    
                        
            
			            
						
						
			
			
			
			
		
    

        
        
        
    
					
    
			
    


    
















    
	
    
	
    
					



			








	
	
	
	



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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Feb 6, 2026 9:01 AM
            
            
						
			            		
      
		
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      Hello,
      

      Thank you for sharing the layout. The layout doesn't look too bad but I do have a couple of concerns.
      

      Is this a 2 layer board? This is OK if the grounding is done correctly. Looks like for the most part it is. We do suggest to have an SGND island for the sensitive nodes like RT, CAPFB, OUTFB, Vc, ITST, PFI, and if possible the VCC2P5 return. These returns are all on the left side of the IC. If there is not any noisy returns in that area it is probably OK. 
      

       
      

      Two things I am concerned about is the VCC2P5 regulator which is the digital supply to the IC. This node is susceptible to noise and next to the SW node. It is suggested to have C11 between the IC and the via, be as close to the IC as possible, and have a good quite return. Noise on the VCC2P5 pin has been known to cause odd issues. Also if the GND for C11 is noisy then it can cause the VCC2P5 voltage to bounce. C11 should be moved. One way to test this out is to remove C11, place it on top of the IC and connect it directly between the SGND and VCC2P5 pins.
      

      The other item of concern is the VOUTSP pin. It is nicely Kelvin connected to the input sense resistor however this pins supplies the Iq current for the IC as well as the current sense. The trace for this pin should be much wider to reduce the IR drop from the Iq current. This can cause the part to hit current limit early. One way to eliminate the current limit is to temporarily reduce the current sense resistor from 50mΩ.
      

      The GND from the bottom FET does go to the DRVCC and INTVCC caps OK. the VCC2P5 trace on the bottom layer looks to be in between the vias for the caps and FET and the EPAD, That should move out of the way of that. 
      

      The switching traces for DRVCC could also be a little wider.
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
				
				
				
		
		
      
			
		
      
	
      

      

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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Feb 6, 2026 9:01 AM
            
            
						
			            		
      
		
										0
					
	
      

		
		
      
		
      
                                
                                                            
      
					
      Hello,
      

      Thank you for sharing the layout. The layout doesn't look too bad but I do have a couple of concerns.
      

      Is this a 2 layer board? This is OK if the grounding is done correctly. Looks like for the most part it is. We do suggest to have an SGND island for the sensitive nodes like RT, CAPFB, OUTFB, Vc, ITST, PFI, and if possible the VCC2P5 return. These returns are all on the left side of the IC. If there is not any noisy returns in that area it is probably OK. 
      

       
      

      Two things I am concerned about is the VCC2P5 regulator which is the digital supply to the IC. This node is susceptible to noise and next to the SW node. It is suggested to have C11 between the IC and the via, be as close to the IC as possible, and have a good quite return. Noise on the VCC2P5 pin has been known to cause odd issues. Also if the GND for C11 is noisy then it can cause the VCC2P5 voltage to bounce. C11 should be moved. One way to test this out is to remove C11, place it on top of the IC and connect it directly between the SGND and VCC2P5 pins.
      

      The other item of concern is the VOUTSP pin. It is nicely Kelvin connected to the input sense resistor however this pins supplies the Iq current for the IC as well as the current sense. The trace for this pin should be much wider to reduce the IR drop from the Iq current. This can cause the part to hit current limit early. One way to eliminate the current limit is to temporarily reduce the current sense resistor from 50mΩ.
      

      The GND from the bottom FET does go to the DRVCC and INTVCC caps OK. the VCC2P5 trace on the bottom layer looks to be in between the vias for the caps and FET and the EPAD, That should move out of the way of that. 
      

      The switching traces for DRVCC could also be a little wider.
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
				
				
				
		
		
      
			
		
      
	
      

      

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