LTC3350 refuses to charge

Hello,

Schematic wise this looks OK. We do suggest not to float the GPI and I2C inputs but that is not likely the problem. Is there any load on the output? This might be layout related. 

Is that the SW node that is being probed in the pictures? 

What is the resistor across the supply?

Is it possible to get onto the PFO pin and see if it is pulling down or open impedance? 

What has changed from the prototype this board? Layout maybe?

Is it possible to share the LTC3350 portion of the layout?

Hi MartyM,

Answers to your questions:

- There is no no load on the output (though the problem is seen when I have a 150mA load too).

- The images are the SW node, it comes to life and then (usually) stops again when I get past ~10V (I guess when I get to the PFI threshold)

- The 1K resistor across the PSU was just to discharge the bench supply when I turn it off (the big output caps in the supply were taking a while to discharge)

- I can probe PFO (I'll have to add a pull-up first I guess)

- Changes from proto were trivial, we had a pull-up from PFO to 12V (a no-no) which was removed and some connector pinouts were altered

- For layout, please see the attached.

Thankyou for your reply. If there's anything else that you would like to see scope / setup-wise please let me know. We are desperate to get a fix for this.

Thanks in advance for your help.

Hello,

Thank you for sharing the layout. The layout doesn't look too bad but I do have a couple of concerns.

Is this a 2 layer board? This is OK if the grounding is done correctly. Looks like for the most part it is. We do suggest to have an SGND island for the sensitive nodes like RT, CAPFB, OUTFB, Vc, ITST, PFI, and if possible the VCC2P5 return. These returns are all on the left side of the IC. If there is not any noisy returns in that area it is probably OK. 

Two things I am concerned about is the VCC2P5 regulator which is the digital supply to the IC. This node is susceptible to noise and next to the SW node. It is suggested to have C11 between the IC and the via, be as close to the IC as possible, and have a good quite return. Noise on the VCC2P5 pin has been known to cause odd issues. Also if the GND for C11 is noisy then it can cause the VCC2P5 voltage to bounce. C11 should be moved. One way to test this out is to remove C11, place it on top of the IC and connect it directly between the SGND and VCC2P5 pins.

The other item of concern is the VOUTSP pin. It is nicely Kelvin connected to the input sense resistor however this pins supplies the Iq current for the IC as well as the current sense. The trace for this pin should be much wider to reduce the IR drop from the Iq current. This can cause the part to hit current limit early. One way to eliminate the current limit is to temporarily reduce the current sense resistor from 50mΩ.

The GND from the bottom FET does go to the DRVCC and INTVCC caps OK. the VCC2P5 trace on the bottom layer looks to be in between the vias for the caps and FET and the EPAD, That should move out of the way of that. 

The switching traces for DRVCC could also be a little wider.

Thanks MartyM,

Those are things that I can try and see if they make any difference. It is a 2-layer board and the bottom side is all GND. I can add capacitance on the bottom side of the board, directly between the pin 23 2V5 via and the GND vias. I'll take a 2V5 measurement with and without this capacitor. If that makes no difference I'll try your other suggestions.

Thanks again

Hi again,

I have made progress. Firstly the 2V5 supply looked clean even with the cap a little distance from the pin. I measured about 60mVpp of clock noise on this supply, but I think my oscilloscope was picking that up from the general setup. I did the capacitor mod and with the cap in the optimal location and I still see the same result.

However, I randomly changed Rsnsc from 8mR to 50mR (4A current limit reduced to 640mA) as I don't need anywhere near 4A in backup mode. My understanding from the datasheet was that this should have no effect upon charging as the charge limit is set by Rsnsi which I have set to 50mR (640mA total input current limit).

With, this change in Rsnsc the issue seems to be resolved. I have done this to 5 boards now and they all start charging as expected when I either slowly ramp up the input voltage or hit them with with the default 12V Vin. When I apply Vin I see the current smoothly ramp up and drop off again when the capacitors are fully charged.

Have you seen the Rsnsc resistor having any effect like this before? Maybe the difference between Rsnsi and Rsnsc shouldn't be too great?

Hello,

I am glad progress is being made on this. I have not seen the RSNSC affect the ability to charge like this before. This might have to do with the fact that RSNSC adjusts the peak current to provide an average charge current in charge mode. With the peak current much higher than the RSNSI limit, I expect the peak current limit is being reached before the RSNSI has a chance to react. That is my theory but will need to investigate. Most typical designs have an input current limit 1A or greater. 

The other possibility is that the larger peak current creates more noise and is causing noise on the VCC2P5 pin. I have seen issues with noise on the VCC2P5 regulator causing odd behavior like this before.  One way to test this out is to remove C11, place it on top of the IC and connect it directly between the SGND and VCC2P5 pins.

Hi, it is definitely not the 2V5 supply as I already did the capacitor on top of the IC and even tried with additional caps and it didn't help (2V5 looked very clean too). It definitely feels like it starts charging then immediately decides against it, so the peak current issue sounds feasible. It also explains why we only see this when the caps are FULLY discharged. With some charge already in them we don't see the issue (lower peak current I assume?) Thanks