[Critical Issue] LTC7804 100% Failure Rate: INTVCC LDO Collapse & Instability

I am experiencing a critical stability issue with the LTC7804 in a synchronous boost configuration (15V to 24V), resulting in a 100% chip failure rate during testing.

Despite following standard design practices and implementing extensive protection circuits, the internal LDO (INTVCC) fails to maintain regulation when driving modern, high-performance MOSFETs, leading to catastrophic failure of the controller.

1. System Configuration:

• Topology: Synchronous Boost (VIN=15V,VOUT=24V,FSW=375kHzVIN​=15V,VOUT​=24V,FSW​=375kHz).

• MOSFETs: Originally Infineon IAUZN04S7N026, switched to Vishay SiR662DP and BSC032N04LS which is used in Demo board.

• Protection Added:

  • External Schottky (B140) on SW node to GND (clamping negative voltage).

  • High-voltage Bootstrap Diode (NSV1SS400, 100V rating).

  • Bootstrap Resistor (RBOOT) tested from $0\Omega$ to $10\Omega$.

2. The Problem: INTVCC Instability
When the device attempts to switch (even under light load of 20mA in Pulse-Skipping mode), the INTVCC voltage collapses significantly, often dropping below the UVLO threshold (<3.3V) and then rebounding with a massive spike (>7V), exceeding the Absolute Maximum Rating (6V).

3. Debugging & Mitigation Attempts (All Failed):
We have isolated the issue to the internal LDO's inability to handle the transient current requirements of the MOSFETs (Qg≈35nCQg​≈35nC), combined with extreme sensitivity to layout parasitics.

• Capacitor Upgrades: We increased the INTVCC capacitance from 4.7uF up to 47uF, and even tried stacking ceramic capacitors directly on Pin 12 and Pin 17 to minimize ESL. The voltage dip persists.

• Bootstrap Resistor: Adding a 3.3Ω to 10Ω series resistor smoothed the charging peak but caused the High-Side drive voltage to sag (staircase drop) due to insufficient charging time during burst mode.

• Isolation Test (Async Mode): We disconnected the TG pin and shorted the Top FET Gate-Source (forcing asynchronous operation). 

• Result: INTVCC still collapses significantly just by driving the Bottom FET (BG).

• External Supply Test: We disabled the internal LDO and supplied 5V externally to the EXTVCC pin. 

• Result: Even with an external bench supply, we observed a voltage drop to ~4.0V at the pin during switching, indicating high internal impedance or path resistance.

4. Conclusion:
It appears the LTC7804's internal LDO and power distribution architecture are too weak to drive MOSFETs , or the chip has zero margin for layout parasitic inductance, leading to immediate destruction of the LDO block (INTVCC measures 17Ω

 to GND after failure).

Note on Support History:
I was previously working with an ADI application engineer on this specific case. However, I have been informed that he has left the company, and unfortunately, he left without providing any constructive solution or root cause analysis.

I urgently need a senior engineer to review this case. Is the LTC7804 simply incompatible with this class of MOSFETs, or is there a known design flaw regarding the LDO's transient response?