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What are the high side and low side gate capacitance values?

Thread Summary

The user is seeking values for C_GATE_HS and C_GATE_LS for power calculations in a buck regulator, which are not provided in the datasheet. The rise time of 300 ns from Table 3 is related to PMBus Interface timing, not the gate rise/fall times. The final answer suggests looking into reducing switching frequency to improve efficiency, which would impact load transient response.
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Category: Datasheet/Specs
Product Number: ADP5055

I am using the power calculation formulas on page 31 of the datasheet, and one of the parameters is C_GATE_HS and C_GATE_LS.

I can't find values for those in the datasheet, so I just used an estimate. Does anyone know what those values are?

Also, for the rise time and fall time, I used 300 ns, from table 3 on page 8. Is that what I should use for rise time and fall time?

  • Datasheet doesnt provide specs on Gate capacitance for high side and low side. 

    Rise time listed in Table 3 is related to PMBus Interface timing. 

     

    Power dissipation section on page 31 of datasheet provides description of different factors that contribute to total power dissipation in the buck regulator. If you would like to look into improving efficiency for your solution, you can  look into reducing switching frequency this would reduce AC loss but would have an impact on load transient response. 

     

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