LTC7000 datasheet has various tolerances for current limit circuit.

I_ISET is 10uA ±1.3uA, or ±13% tolerance, which assuming perfect resistor will cause a V_ISET voltage with ±13% tolerance.
Threshold voltage ΔV_SNS has asymmetric tolerance of +7% / -10% (at V_ISET of 1.2V).
Because ΔV_SNS = 0.05*V_ISET, nesting the V_ISET tolerance to the threshold voltage tolerance give me +21% and -22% total tolerance on current sense threshold, just from the IC.
This seem very loose, is this the correct way to understand this current limit tolerance?
I'm trying to get a better understand of my potential min/max current limit, this is already very wide and does not include any external resistor tolerance.
Please let me know, thank you.