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Current limit tolerances

Thread Summary

The user is concerned about the wide tolerance of the current limit circuit in the LTC7000, specifically the ±13% tolerance on I_ISET and the asymmetric +7%/-10% tolerance on ΔV_SNS. The final answer confirms the user's analysis and suggests trimming R_ISET or using a DAC/voltage reference to achieve tighter tolerance, ensuring the voltage source can sink the 10uA ISET current.
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Category: Datasheet/Specs
Product Number: LTC7000

LTC7000 datasheet has various tolerances for current limit circuit.

I_ISET is 10uA ±1.3uA, or ±13% tolerance, which assuming perfect resistor will cause a V_ISET voltage with ±13% tolerance.

Threshold voltage ΔV_SNS has asymmetric tolerance of +7% / -10% (at V_ISET of 1.2V).

Because ΔV_SNS = 0.05*V_ISET,  nesting the V_ISET tolerance to the threshold voltage tolerance give me +21% and -22% total tolerance on current sense threshold, just from the IC.

This seem very loose, is this the correct way to understand this current limit tolerance? 

I'm trying to get a better understand of my potential min/max current limit, this is already very wide and does not include any external resistor tolerance.  

Please let me know, thank you.

  • Hi, 

     

    I agree with your analysis. However, I do want to note that this is a worst-case scenario over the operating temperature range of the part. Depending on your operating temperature range, your tolerance in practice could be better.

     

    If you would like a tighter tolerance on the current limit, I would recommend trimming RISET to ensure your V_ISET voltage or driving V_ISET with a DAC or voltage reference. If you pursue this option, you will need to ensure that your voltage source can sink the 10uA ISET current to avoid damaging the parts.

     

    Best,

    Blaise

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