LT8316 Bias and FB loops

My response:: to your response.

100W output power is right at max with flyback topology, I would look into using Forward topology 

1. What do you recommend I do to contain the high bias levels.

I am using a Wuerth Flyback for +-24VDC 100W in my 100W design w. 122uH (750811749). Laux is 18-20V.

The bias climbs at PSS (periodic steady state) to 30-31VDC, which is below the 40V limit for Bias .

The LT8316 internal LDO generates 10V and so I am worried the chip has to dissipate unnecessary more power.

The LTSPICE simulation shows 20+volts but I am experiencing 30+V. see scope image.

My hunch is the system has inductive ringing somewhere caused by board design perhaps...

(As a possible solution I am experimenting w a 20/22V UniTVS to clamp the Vaux ringing which seems to be working. UniTVS to leave the negative pulse unaffected)

Any thoughts ?

I agree with ringing on Bias is most likely due to parasitic on Tertiary winding. This could include transformer and layout. Clamping the ringing would be a good start. 

Below the Bias with no TVS. (C3 is Vaux , C4 is bias - scope is 200MHz latest gen 14 bit)

As you can see the Vaux has a plateau of 20.565V but additional ringing causes the Bias to swell to 30V. 

Here after inserting uniTVS, reducing Bias to 22.8V (C1 is VdrainQ1 C4 is Bias)

Channel 4 showing Bias pin is not clearly visible in this plot, but based on your note it seems ringing has been reduced which is what I would expect. 

I have started to characterize the Csnubber size. My measurements show the LC ringing (Leakage inductance)  is right at 4MHz. My original design used a 75p and R510. (-3dB at 4MHz). Basically in the time domain this capacitance must be higher to counter the resonance. At a frequency level this low pass corner (-3dB) needs to shift down toward 1MHz w an attenuation of 12-15dB at 4MHz etc. 

Furthermore (this is relevant for the 50W design only) the Snubber Zener is currently set to 188V. Given the Vin,  N1/N2 ratio of 4, plus the output diodes plus the Vout i get about 280-300V. (Vin min vs Vin max). However the Zener TVS conducts only at about (Vin+ 188VZener which is over 330V). I am planning to further reduce the TVS working voltage from 188 to 150V and possibly to 130V to reset the leakage more efficiently. LMK what you think. 

2. Second question is related to Vfb

Based on the above LT8316 design I have started an alternative version using SSR (versus my original design uses PSR )

ADUM4195-1 feeding secondary to the FB pin (via a fine tune potentiometer), adding a secondary 5V regulator plus an HV network/transistors/zeners to reduce the primary power to 5V etc.. 

Obviously much more complex plus adding a several dollars to the BOM. That said the PSR is ok if the downstream stability requirements are not too stringent.

I have experimented w a one turn potentiometer in the PSR loop to see if the tolerance spread can be compensated after production etc..but it appears this is causing enormous stability issues especially for the FB/VC loop. (frequency is not stable etc.)

Any thoughts about this??

I believe you are looking into using Synchronous secondary rectifier mainly to improving efficiency. 

You can take a look at LT8309 which is a secondary side synchronous rectifier driver

Yes LT8309 is a good choice. The ADuM4195 is targeted toward SSR feedback to the FB pin and not using the tertiary winding for voltage feedback. 

Also eliminating the need for TC pin programing etc. since the diodes are not part of the loop.

I have built a test harness for this and it works well. It assures +24VDC under all conditions,. and allows inserting a potentiometer into the loop. for tuning. etc. 

This is only relevant for 100-140W when using the higher power Wuerth Flybacks. (It is the absolute limit of Flybacks I agree)

 See ripple 

How do I refine the output ripple with this LT8316 design?

The ripple RMS is around 40-60mV (about 0.2%). Ripple Vpp is 200-230mV. 

How can i address this and avoid having it flow downstream?

Thank you for your help.

Between flyback and forward, forward converter has much lower output ripple.

In flyback, output ripple depends on:

1. Layout

2. Output capacitance and ESR

Output ripple can be reduced by adding output capacitors and looking at output capacitor ESR.

You can also look into adding 2nd stage LC filter at the output

Yes I have started to implement an LC filter in the output. (1uH and super low PANASONIC low ESR caps 1000uF w a 2Ohm || resistor to reduce startup current through the inductor.)

Also at 200-220W we will be looking at synchronous Forward controllers. It is part of the PSS5 strategy.

Much more complex design (high BOM costs) even if more efficient and less noisy. (at least 4 magnetics plus a half bridge switcher plus opto/icoupler etc.)

thank you

My response:: to your response.

100W output power is right at max with flyback topology, I would look into using Forward topology 

1. What do you recommend I do to contain the high bias levels.

I am using a Wuerth Flyback for +-24VDC 100W in my 100W design w. 122uH (750811749). Laux is 18-20V.

The bias climbs at PSS (periodic steady state) to 30-31VDC, which is below the 40V limit for Bias .

The LT8316 internal LDO generates 10V and so I am worried the chip has to dissipate unnecessary more power.

The LTSPICE simulation shows 20+volts but I am experiencing 30+V. see scope image.

My hunch is the system has inductive ringing somewhere caused by board design perhaps...

(As a possible solution I am experimenting w a 20/22V UniTVS to clamp the Vaux ringing which seems to be working. UniTVS to leave the negative pulse unaffected)

Any thoughts ?

I agree with ringing on Bias is most likely due to parasitic on Tertiary winding. This could include transformer and layout. Clamping the ringing would be a good start. 

Below the Bias with no TVS. (C3 is Vaux , C4 is bias - scope is 200MHz latest gen 14 bit)

As you can see the Vaux has a plateau of 20.565V but additional ringing causes the Bias to swell to 30V. 

Here after inserting uniTVS, reducing Bias to 22.8V (C1 is VdrainQ1 C4 is Bias)

Channel 4 showing Bias pin is not clearly visible in this plot, but based on your note it seems ringing has been reduced which is what I would expect. 

I have started to characterize the Csnubber size. My measurements show the LC ringing (Leakage inductance)  is right at 4MHz. My original design used a 75p and R510. (-3dB at 4MHz). Basically in the time domain this capacitance must be higher to counter the resonance. At a frequency level this low pass corner (-3dB) needs to shift down toward 1MHz w an attenuation of 12-15dB at 4MHz etc. 

Furthermore (this is relevant for the 50W design only) the Snubber Zener is currently set to 188V. Given the Vin,  N1/N2 ratio of 4, plus the output diodes plus the Vout i get about 280-300V. (Vin min vs Vin max). However the Zener TVS conducts only at about (Vin+ 188VZener which is over 330V). I am planning to further reduce the TVS working voltage from 188 to 150V and possibly to 130V to reset the leakage more efficiently. LMK what you think. 

2. Second question is related to Vfb

Based on the above LT8316 design I have started an alternative version using SSR (versus my original design uses PSR )

ADUM4195-1 feeding secondary to the FB pin (via a fine tune potentiometer), adding a secondary 5V regulator plus an HV network/transistors/zeners to reduce the primary power to 5V etc.. 

Obviously much more complex plus adding a several dollars to the BOM. That said the PSR is ok if the downstream stability requirements are not too stringent.

I have experimented w a one turn potentiometer in the PSR loop to see if the tolerance spread can be compensated after production etc..but it appears this is causing enormous stability issues especially for the FB/VC loop. (frequency is not stable etc.)

Any thoughts about this??

I believe you are looking into using Synchronous secondary rectifier mainly to improving efficiency. 

You can take a look at LT8309 which is a secondary side synchronous rectifier driver

Yes LT8309 is a good choice. The ADuM4195 is targeted toward SSR feedback to the FB pin and not using the tertiary winding for voltage feedback. 

Also eliminating the need for TC pin programing etc. since the diodes are not part of the loop.

I have built a test harness for this and it works well. It assures +24VDC under all conditions,. and allows inserting a potentiometer into the loop. for tuning. etc. 

This is only relevant for 100-140W when using the higher power Wuerth Flybacks. (It is the absolute limit of Flybacks I agree)

 See ripple 

How do I refine the output ripple with this LT8316 design?

The ripple RMS is around 40-60mV (about 0.2%). Ripple Vpp is 200-230mV. 

How can i address this and avoid having it flow downstream?

Thank you for your help.

Between flyback and forward, forward converter has much lower output ripple.

In flyback, output ripple depends on:

1. Layout

2. Output capacitance and ESR

Output ripple can be reduced by adding output capacitors and looking at output capacitor ESR.

You can also look into adding 2nd stage LC filter at the output

Yes I have started to implement an LC filter in the output. (1uH and super low PANASONIC low ESR caps 1000uF w a 2Ohm || resistor to reduce startup current through the inductor.)

Also at 200-220W we will be looking at synchronous Forward controllers. It is part of the PSS5 strategy.

Much more complex design (high BOM costs) even if more efficient and less noisy. (at least 4 magnetics plus a half bridge switcher plus opto/icoupler etc.)

thank you