Hello,
I'm working on a design that needs to support a wide input range of 18 to 50V Input. I'm using the LTC4364 as an Ideal Diode Or'ing circuit with Inrush protection, OVP, OCP. The datasheet recommends for inrush protection to add a capacitor from HGATE to Ground to control the inrush current. This however, causes the blocking FET to disable when a fast input transient occurs due to the sudden change on the source node. The datasheet also recommends that the minimum capacitance should be 6.8nF to ensure stability of the overcurrent and overvoltage loops.
My questions are:
1. Is this 6.8nF really a minimum requirement on the HGATE pin?
2. Can I instead place my inrush capacitor between the gate and source nodes rather then gate to ground. This will eliminate the issue of turn-off when a input voltage transient step occurs.
Ask can i put a cap where C5 is, and not have a capacitor where C15 is in the spice model below.
Simulation of what happens with a capacitor where C15 is:
