Charging Problem(Charging Time)

Hello,

Things that affect the charging time. dt = CdV/dI. If the capacitance is the same, the set VCAP voltage is the same, then the only difference will be the charge current. The charge current is affected by a few things. The total resistance between ISNS_CHG and ISNSM multiplied by the total input current including the load. If the voltage across these pins start to increase close to 32mV then the charge current will be reduced. If there is a load that causes the charge current plus the load to approaches the maximum set input current, the charge current will be reduced. The full charge current is set by the resistance across the ICAP and VCAP pins. This sets an average charge current based on a 30% inductor ripple current. If the inductor is sized to produce a much larger ripple than the average charge current will be reduced. One of the most common issues is the layout. How close does the layout match the demo board? Were the recommended PCB layout recommendations listed in the datasheet followed? If the current sense resistors are not Kelvin connected or shared with other nodes than the voltage observed across either the input current sense resistor or the charger current sense resistor could be incorrect resulting in a lower charge current. Another problem could be noise being injected into the current sense resistor. This noise can also cause the voltage across the sense resistor to be higher than what it actually is and reduce the charge current. 

I should mention one more thing. If for some reason the shunt regulator turn on because one of the cell voltages approaches the shunt regulation voltage (2.7V is the default) then the charge current will be reduced to prevent the high capacitor from exceeding the shunt regulation voltage. 

Hello,

Things that affect the charging time. dt = CdV/dI. If the capacitance is the same, the set VCAP voltage is the same, then the only difference will be the charge current. The charge current is affected by a few things. The total resistance between ISNS_CHG and ISNSM multiplied by the total input current including the load. If the voltage across these pins start to increase close to 32mV then the charge current will be reduced. If there is a load that causes the charge current plus the load to approaches the maximum set input current, the charge current will be reduced. The full charge current is set by the resistance across the ICAP and VCAP pins. This sets an average charge current based on a 30% inductor ripple current. If the inductor is sized to produce a much larger ripple than the average charge current will be reduced. One of the most common issues is the layout. How close does the layout match the demo board? Were the recommended PCB layout recommendations listed in the datasheet followed? If the current sense resistors are not Kelvin connected or shared with other nodes than the voltage observed across either the input current sense resistor or the charger current sense resistor could be incorrect resulting in a lower charge current. Another problem could be noise being injected into the current sense resistor. This noise can also cause the voltage across the sense resistor to be higher than what it actually is and reduce the charge current. 

I should mention one more thing. If for some reason the shunt regulator turn on because one of the cell voltages approaches the shunt regulation voltage (2.7V is the default) then the charge current will be reduced to prevent the high capacitor from exceeding the shunt regulation voltage.