Category: Hardware
Product Number: ADM1270
Hello,
we have some issues during ESD testing. We use the ADM1270 as an E-FUSE for several supply voltages.
In case of ESD pulse on any of our IOs, the PWRGD pin is triggered. We tried to disable the UV, OV and FB_PG. This happens only to one of the ADM1270. All ADM1270 circuits are implemented identcally.
We have the assumption that the GND connection (Layout) of the ADM1270 with issues is not the best.
The FAULT is not used. The PWRGD pin is pulled to VCAP with 332k and triggers a MOSFET BSS138. The generated signal by the MOSFET is pulled up to the supply voltage (same as for the ADM1270)
Are there any recommendation to harden the PWRGD pin?
There are given different current values/loads for VCAP:
- 0uA < IVCAP < 1mA, CVCAP = 1uF (page 3, Rev. A)
- do not apply a load to the VCAP pin greater than 100 µA (page 17, Rev. A)
Which one does apply?
Best regards, Alessandro
