Boost region duty cycle jitter

Specs:

L = 15uH
Cout = 8x 180uF
CIN = 5x 180uF

attached is SW2. 500ms per division. Looks like it holds target voltage 42.6v for 900ms and drops to about 41.8v before resetting to target voltage over 500us, repeating. The scope image is indeed 2V per division, I just put the vertical-zero waaayy down off-screen so I can magnify the ripple. Its 42.6V where the signal is flat.

I had a lot of ideas why its doing this and they are all having no affect (checking VINR, FBIN, FBOUT, VC, etc). I changed my 10K at VC to 20K and 5K with no noticeable affect. Im just tweaking anything at this point to see any change in this behavior.

attached is at 64Kohms for VC. The picture before was with 20Kohms which was the same roughly for 5k, 10k.

I dont know what to do with that information right now but it affected the signal. Also doesnt mean that I am on the right track, this change can just be the results of altering response time and stability with the R value of VC and is simply superimposed over the problem I am having.

here is 10k, 8nF on VC with no load.

With load it looks like the first scope picture I posted.

However I did notice it started out much more smooth and then approached the first scope pic sent. I was so happy like I fixed it and then it came back. Sad.

Perhaps vc wont fix it, I just delayed it from coming. perhaps if I push it out far enough it will never come? Im just hoping someone on this forum might recognize what this signal means.

If I mash my finger around the following resistors (which are all grouped together) I do influence this duty cycle jitter. Also, I cant provide a picture of the jitter because my camera captures one instance in time which, is not jittering. But I am sure you can imaging the duty cycle havign to change to create that varying output voltage.

Also the load is a simple 10ohm resistor I can turn on and off.

These are all 0603 so I cant precisely figure out who it is with my finger but I think its more on the right side than the left.

The right half of parts:

• 1nF, 1nF, 1nF for the CSP CSN

• 1 of the 4.7uF caps to INTVCC, GATEVCC.
• And the IMONIN and IIR cap and resistor 15.4k, 0.1uF.

The left half of parts:

• SDHN resistors 64.9k, 30.9k
• and the FBOUT resistors except R_FB1

I started throwing my probe around to see if the tiny capacitance of my probe would adjust the duty jitter. The I hit Fbout and it blew the chip so I have to replace that another day. Tapping CSP CSN caps did nothing. Tapping SDHN did nothing. And thats all i got to do.

Makes sense I cant just probe FBOUT, but thought I would try. I also cant probe RT if that means anything. There's no damage doing RT but it makes the LT8490 go wild buzz and sputter.

I doubt INTVCC is relevant because that would affect both buck and boost stages. The IMONIN and IIR stuff is for input, but would be interesting if thats somehow affecting output? FBOUT is there and would have the most obvious influence, but it probably wouldnt be wise to put a 22pF on FBOUT to suck away noise seeing as just my probe popped it. But then again my probe is injecting some noise too with is 4 inch ground wire.

Its just speculation at this point. These parts may have no relationship and simply me touching them just affects the whole system and not the problem alone.

This is a key observation:

There is the duty cycle jitter observed between each period which we are around 185Khz. This jitter is present at all times. The ripple seen in the previous images is a separate behavior because even while the output ripple has that flat stable voltage (before the quick drop) the jitter is still visibly present on a pulse to pulse bases. The ripple is 1000ms+ period while the duty jitter is the period of the operating frequency.

They are likely related to each other but its possible they are not. The pulse to pulse jitter is more important since that scales with output current and prevents me from reaching full power while the more macroscopic ripple doesnt seem to affect performance at all.

Going through the datasheets thoroughly. I found some explanation of this scope pic I had shown earlier. I match it perfectly.

which means this part of the signal is what I am seeing on the VOUT in normal operation. I typically only get that flat-decelerating ripple part but its definitely the same signal because my signal is the same period as the one in the datasheet.



I guess I can write off this signal as "normal" and unrelated to the boost region duty cycle jitter issue.

This is a funny issue where I start probing "everything" and seeing interesting behaviors and I dont know if they are good or bad or always have been there. I just know the duty jitter is bad. I see that I can insert a video so I'll put on the new IC and record a few seconds of the jitters and post.

Duty jitter (still image) on SW 2 node. M3 and M4 are jittering together so for simplicity I am showing switchnode 2 (SW2) boost region. Also any over-undershoot you see is just my probe with 4 inch ground wire picking up noise. The waves are perfect squares with a probe spring taking the measurement.





Here is a short video showing the jitter. The SW1 does not do this so I know its not my scope trigger or probe.


This is the clkout pin while I had switching disabled. I dont know if it normally does this but its jittering around too.

Something to consider. Maybe I'll play with my sense resistor filtration.
Source: https://www.analog.com/en/resources/app-notes/an-139.html

I removed the 1nF coupling CSP and CSN and saw no affect. I removed the 1nF CSP bypass to ground and the 1nF CSN bypass to ground and did see more duty jitter.

I put 47pF caps for the two bypasses to ground and saw it return to as if it was 1nF until I got to higher load and the jitter got really bad.

So that is interesting that I am affecting the jitter. But it doesnt seem to get 'better', just 'as good as it was before' which 'aint good enough'.

Plans for tomorrow:
The datasheet says to not have an RC greater than 30ns. So I will put a 2nF down (more like two 1nF stacked on top of each other... but hey!) and see what happens. I can reduce the 10ohm to something smaller and try various RC values.

doing some reading before the sun is up for testing.

This was a big wow moment: Picture below, and yes the LT8490/8705 is a peak current mode converter: source: https://www.ti.com/lit/an/slua747a/slua747a.pdf?ts=1752558982927



A key difference between my working boards and this more jittery one has been I increased the inductor from about 5uH to 15uH. The jitter is present in the previous rev but barely noticeable and is no concern at full power output. With the inductor increased by a factor of 3, I now get significant boost side jitter because (theoretically) it shallows the slope of the resistor current which in tern shallows the slope compensator ramp and so any noise is more easily perceived (because the distance between the slope compensator and the measured signal are closer to each other and for more time). that's fascinating.

This feels consistent with the LT8705 datasheet saying that the inductor current sensing measures the peak during boost and the valley during buck. Well, I would expect the valley to be less noisy so my buck side is clean (which it is) and the boost side to be more noisy (and it jitters).



The section in the LT8705 datasheet about the filtration of CSP/CSN I feel is a bit misleading or perhaps I am misunderstanding it. It says the RC product cannot exceed 30ns right after talking about the common-mode filter configuration. This lead me to believe I cannot have my common mode caps greater than 3nF with a 10ohm resistor. But I see in the LT8490 datasheet in the last few pages they used 10nF caps with the 10ohm resistor. So... does this mean they are only talking about the differential cap that cannot exceed RC of 30ns? Well, I presume they tested those examples so I will give it a shot. Its similar to my system: high voltage, high power, and a 15uH inductor... I mean the worst that can happen is I blow the mosfets and LT8490 again. So lets try bigger common-mode caps.




I'll be back with results, good or bad!