Post Go back to editing

LT317A Loop stability design

Thread Summary

The user asked how to simulate the Bode plot for a circuit similar to the one in the LT317A datasheet to find the phase and gain margin using LTspice. The final answer confirmed that the circuit worked well with the .fra component placed in series with the upper sense resistor, but adding a 10uF capacitor in parallel with the lower sense resistor prevented the 0dB crossover from being found. The accompanying answer provided a circuit diagram and an LTspice file for reference.
AI Generated Content
Category: Software
Product Number: LT317A
Software Version: LTspiceXVII and/or LTspice24

How can I simulate the Bode plot for this device(circuit) to find the Phase and gain margin using LTspice software?

My circuit looks similar to the onces shown in the datasheet.

Input voltage: 12V (9V to 12V)

Output voltage: 5V

Output current: 150mA to 1A

Regards

Udo

  • It is easiest to use the FRA tool in LTspice, but if you have a physical Bode plotter, I would just put the injection resistor in the same place as the FRA tool.  The injection resistor can even be ground referenced.   

    sim ckt and result_1.png

    LT317A_5.asc

  • LT317A_LTspiceXVII_Udo.ascThank you very much for your file which I tried to simulate. I'm surprised where you placed the .fra component. Traditionally a stimulator is placed in series to the upper sense resistor. Nevertheless, your circuit worked well, provided the lower sense resistor has no paralled capacitor. In the LT317A datasheet, very often a 10uF is connected in parallel to the lower sense resistor. If I do that in your circuit, the 0dB crossover is not found.

    Meanwhile I've used LTspiceXVII as well, and the acsweep was placed in series to the output.

    I would like to send you this file for inspection, but I don't know how to attach this file.

    Best Regards

    Udo