LT4363 Gate pin issue

WoodyLai said:

During power-up, we observed abnormal behavior on the GATE pin, as shown in the attached waveform. In an attempt to reduce inrush current, we removed the large output capacitors (PCE1, PCE2, PCE3, PCE6). After doing so, we noticed that the GATE pin behavior differed from the original condition when those capacitors were present. Could you help us understand the reason for this change?

I think you are hitting current limit with a really short timer.
(Current limit is folded back from 10A to 5A when V_OUT is low)
TMR needs to be at least 10nF. See pin description on page 8 in datasheet (DS).

Also, PD7 (D_GATE) is facing the wrong way. It's a path around PR32 (R_GATE) during startup.

WoodyLai said:

2. In the case of an overcurrent fault, we observed that the FLT pin is pulled low. If we then pull the SHDN# pin low to disable the LT4363, and later pull it high again to re-enable the device, will this clear the fault condition and restore normal operation?

I think so. From page 13 of DS:
"For both the LT4363-1 and LT4363-2 the FLT pin goes high in shutdown and is cleared high when power is first applied to VCC. If FLT is set low, it can be reset during the cool down phase by pulling SHDN low for at least 1s/μF of C_TMR."

Thank you for your previous response.

We have a follow-up question regarding the FLT pin behavior.

In our current design, the system fails to power up when VIN = 32V. We suspect this is due to an inrush current at startup, which might be triggering an overcurrent fault, causing FLT to be pulled low.

To address this, we attempted to restart the LT4363 after power-up by toggling the SHDN pin low, hoping to bypass the inrush condition. However, as shown in the attached waveform, FLT remains low even after the restart.

This raises our main question:
Does this mean the fault is not caused by inrush current, as we initially suspected? Or could there be another fault condition triggering FLT?

Best regards,

Woody