We are using the IC LTC3260IDE#PBF for one of our applications - we are using both the LDOs - LDO + and LDO -.
We are deriving the output of +17 and -17V from LDO+ and LDO-.
However, after designing the proper feedback resistor network in our application is - R2 and R11 combination is - 820K and 62K which will give us the +17V and -17V.
This is on the design perspective.
Our parameters:
Vin - 24V
Rt Freq set at - 500KHz.
Expected LDO+ output - 17V
LDO- = -17V
Measured -
We are measuring LDO+ = 17.02V - which is currently okay.
The problem we are facing is with LDO- is that the voltage is higher than expected which is = -17.6V to -17.85V.
I have attached the ref image of the application schematic which is followed exactly.
Now here are some inferences from Lab testing:
1. The frequency at C+ and C- pin in developed board is around 515KHz as opposed to 500KHz which is the setting from RT pin to GND.
2. The Voltage is +17V on LDO+ and is behaving properly with Load regulation also (Varied the load to consume until 100mA).
3. The no load and the with load conditions the LDOs are behaving same.
Can you please help us with the trouble shooting of this issue - will the frequency change the output if so how?
How can we mitigate this?
