LT8357 SPMS Flyback: Glitches trigger over current faults cyclically

Hi Michael,

First of all, thank you for the excellent pictures and explanation of the problem. Everyone should use the above as a style guide.

I think, what happens here is that when the FET is turned OFF, the drain voltage shoots quickly up due to back-EMF. That voltage rise couples to gate through Cgd and turns the FET ON again for a short moment. You need a hard clamp to the gate to prevent that. 100 ohm for the gate resistor R4 is probably too large. The original 5.1 ohm should suffice. You explained that with the original resistor, the desired output voltage was not reached. I wonder, could you provide new waveform plots with the 5.1 ohm R4?

Cheers, heke

Dear Heke,

thank you very much! I already felt a little embarrassed, having noticed the first typo in the subject line about 5 seconds after posting ;-)

I currently do not have a sample that has all identical components except for the gate resistors, so I propose two ways to go ahead here.

1. Have a look at the drain voltage on the circuit from the my previous posting to plausibilize the glitch coming from an undesired drain-to-gate feedback.
2. Analysing measurements that I took prior to the gate resistor modification, though not as comprehensive as in my previous posting.

Drain voltage

The figure below shows the gate voltage at CH1 (yellow) as in my previous post. CH2 (blue) is the voltage at the drain this time.

Zooming in near the end of the burst, I get the curve as shown below. I measured a distance ∆X between the rising edge of the drain voltage and the start of the glitch of about 740ns.

Now I scroll towards the middle of the burst, keeping the time base identical, as shown below. This time, the time difference ∆X is about 459us, i.e. significantly larger/different from what I see near the end. If the glitch is caused by undesired feedback from the drain to the gate, I would not expect such a huge delta, especially because the signals do not look particularly noisy between the rising edge (AX) and the glitch (BX).

Prior measurements

Prior to the PCB modification, the gate driver looked like this. The rest of the circuit is unmodified and corresponds to the initial schematic I posted.

The following figure shows the voltage at the gate at CH1 (yellow). CH2 (purple) this time shows the amplified voltage from a magnetic field probe (Langer EMV RF-U 5-2). The first thing I noticed is that the burst here is about 400 us long, whereas the burst after the modification is 1.67 ms long.

Zooming in again, the pulse and the "glitch" look like this. The distance between the falling transition of the pulse on CH1 and the rising edge of the glitch is is approx. 3 µs, which is the same order of magnitude as the "middle of the burst" zoom picture from the "drain voltage" section.

Unfortunately I did not take any screenshots from the voltage output, though I remember that the voltage never went above somewhere around 40V-44V.

My conclusions are:

• The distance between the pulse and the glitch is varying, and can be comparably long.
• The curve shape between the pulse and the glitch looks pretty clean to me.
• I have some suspicion that the glitch might be coming from the LT8357 itself (possibly because some preceding effect we haven't discovered yet triggers an error in the gate driver circuitry?). Is that plausible to you? How would you test this hypothesis? And, more importantly, what can I do to further track down the cause in this case?

Thank you very much again!

Michael

Hi Michael,

Good stuff! Based on your observations, I'd agree that the extra pulse is originated from inside the chip (Measuring the waveform at GATE_N, GATE_P while having the 100R resistor would confirm that). The internal logic (probably the SR-latch just before the gate driver) gets confused for some reason.

There are a few things that came into mind that you could try:

1. Capacitors C2, C9, C10 seem to be on the other side of the board. Could you try soldering some extra capacitance straight from the pins 10 and 12 to ground (10 may be difficult)?
2. Try increasing the voltage for VIN. Currently VIN seems to be same as INTVCC (+5V) which means that the internal LDO is operating in "pass-through mode". Some LDO's do not work well in such condition. Also probe the INTVCC pin with an oscilloscope to see if there is any unwanted activity.

I hope these make a difference.

Cheers, heke

Hi heke,

thank you!

I have measured the voltage at the GATE_N/GATE_P controller output and can confirm that the glitch originates from inside the chip. In the figure below, CH1 is the actual gate again, and CH2 is measured at the outputs GATE_N and GATE_P which are connected together before the 100R resistor.

Correct, C2, C9 and C7 are on the other side of the board. I have soldered a 100 nF capacitor between VIN (Pin12) and the GND isle (near C1/R2). The following two screenshots show the voltage at INTVCC (Pin10) after the modification.

• INTVCC reaches 5V (with VIN=5V).
• The measurement tool in the oscilloscope shows the INTVCC peak-to-peak voltage of around 500 mV (depending on the horizontal scrolling, sometimes a little more and sometimes a little less).
• The pulse bursts do not get significantly longer, and I interpret this as not showing a significant improvement of my issue. (As a side note, there is in general some jitter in the length of the burst.)

For reference, here is the VIN voltage before adding the capacitor:

And here is INTVCC before adding the capacitor:

Would you consider the shape of INTVCC and/or the VIN voltage an issue after my observations? Right now, the 5V VIN is generated from the 3.6V VBAT using another small SMPS.

I was in fact asking myself why the datasheet states 3V as the minimum VIN operating voltage on page 2 under "Electrical Characteristics". I had initially assumed I can power the LT8357 directly from VBAT, but first simulations showed a similar Vout ramp-up and Soft-Start problem as I have now, which disappeared in the simulation when raising VIN above 4V. However, the simulated pulse bursts at the gate look very different from what I measured (bursts consist of only three pulses, very high duty cycle, no glitches), so I would assume that this insight I got when designing the circuit cannot help me here.

Have a good weekend!

Michael

Hi Michael,

I hope you had a good weekend.

Yes, I noticed the same spec in the datasheet. Vin can go as low as 3V. I do not know what that actually means. It could be that the logical operation of the chip is guaranteed on and above that. INTVCC curve on page 6 (second graph) starts from VIN=6V which faintly contradicts with the page 2 specs.

I'd say that the 500mV ripple at INTVCC may be problematic. The sharp rise and fall edges may confuse the digital logic. Due to that, I wonder, could you try the following two tests:

- Apply 6 volts to the VIN from an external supply. The TPS61222 should be fine with that (you can keep it powered up). Do not go higher than 6V. Will the ripple at the INTVCC get reduced?

or

- Short the INTVCC to VIN. As both are then 5V, the internal LDO is by-passed and is idle. How do the supply and gate voltages look like in that case?

You were right. The spike at the gate voltage clearly shows that it is originated from the chip. Nice measurement.

Cheers, heke

Hi heke,

yes, thank you! I hope your weekend was good too.

I just performed the two tests. As I only have one lab power supply, I connected a Li-Ion 18650 cell charged to about 4.1V to VBAT, which resulted in a slightly longer pulse burst length than with my lab power supply, which was configured to 3.6V.

Test 1: 6V from external supply at VIN

To have a good comparison, I started measuring the previous setup, i.e. the 5V generated by the TPS61222. CH1 this time is the voltage at GATEP+GATEN output, CH2 is the voltage at INTVCC, and CH3 is the voltage at VIN.

With VIN = 6V from my lab power supply, the output looks like this:

Zooming in, the Vpp at INTVCC (CH2) looks much less concerning to me.

Test 2: INTVCC shorted to VIN

Here, CH1 is the voltage at the transistor gate (not the gate driver) again. Sorry for the confusion. CH2 is the voltage at Pin10/INTVCC.

Another idea

When I had a closer look at the pulses at the GATEP/GATEN output, I was thinking in a completely different direction too. The three pictures show three subsequent pulses, and I saw that the pulse length is pretty identical, whereas the duty cycle flips from "very high" to "very low" every other cycle. Could it be that the "glitches" are not caused by electrical problems by itself, but that the control loop is not stable?

Thanks,

Michael

Hi Michael,

Thank you for your good feedback.

OK, Although the supply line looks now better, it's unfortunate that it did not heal your circuit. Now it is getting really mysterious.

The duty-cycle variation that you are observing may be explained by the oscilloscope trigger event. Sometimes it triggers at the main pulse edge, sometimes at the ghost pulse edge. Try with a bit wider time span (showing multiple cycles) to see if that is the case.

There is again a few things you could perhaps try (sorry for multiple shots into dark, but just need to get something to clutch at).

- You explained that the mode does not make difference. Do you see any, even subtle, change per MODE setting?

- If you change the feedback ratio (to FB pin) will something change?

Cheers, heke

Hi heke,

thank you for keeping up with the issue!

Just to clarify, the the pictures from "Another idea" were zoomed in from the same capture, where I triggered at the start of the burst and was able to capture until the end of the burst. Zoomed out, it looked pretty much like the first picture in "Test 2" with only CH1 enabled.

I found an application note titled "How to implement a Soft Start in a Flyback" from another controller supplier, and the document mentioned that increasing the soft start time may be a potential solution to cyclically hitting overcurrent protection loops. So I tried to replace C3 with a 1µF capacitor (was 100 nF), and it seemed to significantly improve the performance.

CH3 shows the output voltage without load. (I did not use CH1 or CH2 because the probes have ground springs mounted, and CH3 has a crocodile clamp.)

This is reproducible on one board with all the modifications made as described, but failed on the second sample without all the modifications (and without some other fixes before I started the topic, which I haven't mentioned). I will try to make the same changes, when I get time to get some missing components.

Later I tried to measure the gate driver pin (CH1) and soft-start pin (CH2) too. The good news is, the pulse burst is significantly longer (> 60 ms now, compared to < 2 ms previously) and is able to reach the target voltage without any over-current triggerings. Well, almost. Soft-Start at CH2 seems to have one period with a falling slope (sorry for the bad Y axis scaling), though I suppose that is another issue related to controlling the load.

Before finding that document I mentioned before, I had imaged that the control loop regulating the transformer current will regulate to the maximum configured current (i.e. 60 mV voltage drop) until the target voltage is reached, but would not trigger the over current protection. Now my educated guess is that if the output at the error amplifier is too big, the control loop does not work well. The soft-start mechanism seems to be used to approach the target value smoothly thus avoiding too big error amplifier outputs.

However, I cannot confirm my assumption with simulations. No matter how small I select the SS capacitor in LTspice, I do not see such flipping of the duty cycle from "very low" to "very high". I did notice that for larger soft-start capacitor values, the output voltage increases linearly (after the "steps" at the start), whereas for small capacitor values, Vout looks like a saturating exponential function.

I have not tried high-level designs using LTpowerCAD, as I don't have Windows, and an installation in Wine failed. Would you think using LTpowerCAD would get me more accurate results / good design recommendations that I wouldn't be able to validate using LTspice?

Answering your questions:

• As for the MODE: Honestly speaking I have not tried playing around more now than I did before. The datasheet on page 10 says "Before the SS pin rising above 1.55V, the control logic forbids synchronizing from external clock and disables the Burst Mode operation and spread spectrum frequency modulation.", and, afair, my SS voltage was always below 1V.
• As for the feedback voltage. I was turning the potentiometer  but did not go the limit (I have used Bourns trimmers that should have 25 turns in total, and I wanted to avoid damaging the trimmer because I don't know when to stop). Within what I tried, I obviously saw a change in the final output voltage, but no reduction soft-start loop cycles in general.

I would see this as a reproducible fix if I get my second sample working too, ideally without having to change the gate driver circuitry here too. If that works well, would you see anything else to do? Or can I say I'm done?

Thank you again!

Michael

Hi Michael,

Thank you for your illuminating takes.

My apologies for a short response earlier (my wife said "dinner's ready". That overrides everything...).

Now, your tests with the soft-start gives a good direction. Your earlier measurement of Drain voltage shows that during the start-up the converter is in continuous current mode CCM (the Drain voltage does not fall back to Vbatt during the OFF state). In that mode the loop may not be stable (as you anticipated). The reference voltage is rising faster than what output voltage can follow. I'd say (hopefully correctly this time :), that slowing down the soft-start ramp is the way to go as it seems to work.

The "ghost" pulse is probably merely a start of a new cycle which is the interrupted by the over current detect. The over current is due to entering to the continuous current mode during previous cycle (which still leaves some doubt, the drain current plot, i.e. the voltage at SENSE pin, remains oddish). Can you check that the diode D1 (part of the snubber) is installed correct way around)?

I have not used LTpowerCAD, thus with regret I cannot give an answer.

Cheers, heke

Hi heke,

no worries at all, in particular when there are non-maskable interrupts. I am thankful that you dedicate your free time to help me solve my circuit issues :-)

Today a friend helped me with some small circuit fixes on the second sample for reproducing my results, such that the circuit is as depicted in the initial schematic, with the following differences

• the gate driver resistors are still as shown under "Prior measurements" (GATEP <--> 5.1 Ohm <--> transistor gate, and GATEN directly connected to transistor gate),
• and the SS capacitor is changed from 100nF to 1µF.

First, I measured the output voltage (CH3) and the voltage at the FB input (CH2), and can see that the output voltage saturates before reaching the configured target voltage.

Then, I measured the voltage at the gate, the current sense resistor, and the drain. The first following picture shows the zoomed-out view for reference, the second one is zoomed in at the middle of the burst. The first good observation is the burst length of about 2.15ms, which is much better compared to the "Prior measurements" burst length of about 400µs. I chose the "Prior measurements" as comparison where I took measurements of the first PCB sample before the previously described modifications, which should be the same as the second sample now.

The glitches at the current sense resistor are a lot higher at the falling gate transitions than at the rising ones, which was to be expected because there's currently no resistor between GATEN and the gate at the second sample. So one preliminary conclusion is that I definitely need a resistor at GATEN.

One curious thing I have also seen before, but not really noticed till now is the 105 mV SENSE Over Current Threshold voltage from the datasheet is exceeded a lot of times before actually triggering the overcurrent fault. I'm wondering if it could be of any help to know what actually triggers the overcurrent fault so I can mitigate it in a more focused way. However, I have no idea how to get more insight in this regard.

As for your comment about the Continuous Current Mode, I would interpret the figure above that the mode changes from CCM to DCM/Light Burst Mode when I compare it with the datasheet figures on page 5. Though I am not sure if there are further conclusions to draw / ideas for improvements.

How do you actually come to the suspicion that the snubber diode polarity may be incorrect? The pin marked with a bar (should be the cathode, if I'm not wrong) points to the RC part of the snubber circuit, I think that is consistent with the schematic.

Looking at the end of the pulse burst in the following figure, one further surprising thing I noticed is that the linear current increase during the transistor on-time does not reach anywhere near the 60mV regulation voltage, so this makes me wonder why the LT8357 decides to make every second pulse that short anyway (and why only every second pulse, because the high glitches are there for all pulses).

The next things I would try is (not sure about the best order, though):

• modify the GATEN/GATEP network again, starting with short-circuiting GATEN/GATEP and cutting the direct connection between GATEN and the gate, and seeing whether this change in combination with the 1µF soft-start resistor leads to significant improvement, and if not, go back to 100R. Not sure if there's a better way to figure out good values, other than trial & error?
• Decrease the value of the current sense resistor.

When I designed the previous circuit/PCB revision (not mentioned here) I used R_sense = 60 mV / (saturation current from datasheet), and the datasheet says on page 20 that the final resistance should be lower(!) than the calculated resistance. I went with R_sense of 2/3*60mV/10A=4Milliohm (10A saturation current at https://www.we-online.com/components/products/datasheet/750032052.pdf). I did not understand why to the actual resistance should be lower than the nominal value, as this may lead to exceeding the saturation current and causing current peaks, so I went the other direction and chose 12 Milliohm for this sample revision, assuming that there is enough margin for the core not to saturate. If the current sense curve would look similar to the previous plots but could transfer more energy per cycle to the secondary side, this may already allow to reach the target voltage while keeping the gate resistors low?

I will be out of town during the easter weekend, so my response time will be a little lower the next days too. Happy easter holidays!

And thanks again,

Michael