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Review Request: ADP7102 and ADP7182 +-2.5V Implementation

Category: Hardware
Product Number: ADP7102

Hello Analog Devices Engineers,

I am implementing the ADP7102 (+2.5V) and ADP7182 (-2.5V) LDOs to generate ±2.5V rails for an op-amp circuit. The op-amp’s total current consumption is expected to be no more than 20 mA. I would appreciate feedback on my implementation to ensure proper operation (I'm somewhat new to designing analog circuitry.)


Implementation Details:

  • Power Setup:

    • ADP7102 provides +2.5V relative to VGND.
    • ADP7182 provides -2.5V relative to VGND.
    • Both LDOs receive +12V (for ADP7102) and -12V (for ADP7182) as input voltages.
    • EXTERNAL_PWR_VGND is supplied by GoldPoint Level Controls' VG2 circuit.
  • Enable Pin Configuration:

    • I want the LDOs to be always on.
    • I have tied the enable (EN) pins to VIN and would like to confirm if this is correct.
  • Input/Output Capacitors:

    • I have implemented 10 uF ceramic input and output capacitors based on the recommendations from the datasheets. The datasheet suggests a lower capacitance value, but because my capacitors are under a bias, I've increased their capacitance such that their effective capacitance is close to the recommended value of 2.2 uF.
    • I would like to confirm that I'm using the best capacitor value and type -- would you recommend additional capacitors or use of capacitors with a different ESR value?
  • Bleed Resistors:

    • I have added bleed resistors to ensure the LDOs consume a minimum load at all times.
    • I would like to confirm whether these resistors are necessary (i.e., if I have to consume a minimum load -- not consuming a minimum load has been a problem for me with other LDO's) and, if so, whether their values are appropriate.

Request for Feedback:

  • Are my enable pin connections correct for keeping the LDOs always on?
  • Does my capacitor selection ensure proper stability and transient response?
  • Are my bleed resistors necessary, and are their values reasonable?

I have attached a screenshot of my schematic showing the full implementation for reference.

I appreciate your time and expertise—thank you in advance for your guidance! The schematic is below:

Thank you for your time and expertise,

-Arjun