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SuperCaps not charging

Category: Hardware
Product Number: LTC3350

I have read through the other posts regarding the LTC3350 and am having a similar issue to others.

The system is 24V in 24v out.

The Chip powers up and appears to be functioning as intended apart from the 4 x 40F (3V)  supercaps not charging. 

PFI is above the threshold (1.17V) at 2.04V however upon reading the PFO pin it is low indicating that this does not appear to be true. (Screenshot 1 of PFI on startup vs Screenshot 2 of serial output of PFI pin.)

RPF1 was changed from 820K R to 499K R reducing the threshold voltage from 21.6V to 13.6 V in an attempt to solve the PFI issue, to no avail. 

Switching and 2.5V line appear stable. 

Registers appear normal. 

Any help is appreciated, please see attached screenshots. 

PFI pin on startup

Serial output of PINs + external current sense IC reading. 

Registers 

SW pin 

Input Pin 

VCC2P5

Schematic 

(RPF1 is now 499K not 820K) 

Layout bottom 

Layout top 

  • Hello,

    Thank you for all the information. The schematic doesn't look OK. The Vc cap should be reduced to about 1nF for this application but that is not what is causing the issue. 

    What is the output current expected in charge mode and backup mode? I see the input sense resistor is set to 1A and the peak boost current is set for about 3.6A. The boost peak current needs to be more than about 2.5x to than the maximum output current during backup. Maybe more depending how long the backup needs to last. Obviously, this is not the problem either since it doesn't reach backup mode. 

    With VCAP set to 10.87V the part can only charge up to about 10.8V max with the shunt regulator set to the default value which I see it is. The shunt regulator should be increased to at least 50mV/cap, 200mV total to allow the caps to charge all the way up. The shunt regulator typically starts turning on about 50mV below the shunt regulator setting. It is best to set the shunt regulator at the maximum voltage the capacitor is allowed to be set to. Typically that is 2.7V, sometimes 3V for cooler ambient temperatures. 

    Since this is a 500kHz design, it is best to view the SW node with the horizontal setting at 10us/Div to see how it is behaving. 

    The noise on the PFI and 2.5V will need to be viewed around the same time frame. 

    Is it possible to capture PFO with VIN rising and with about 100us/Div. 

    The layout could use some improving. 

    1. SGND should be isolated from the power ground except for the connection from the pin to the EPAD as shown in the below. The SGND should form an island to isolate the sensitive nodes from the fast switching return paths. 
    2. I could not follow the sensitive traces very easily, but I can see from the placement that the OUTFB divider is on the opposite side of the IC as the OUTFB pin. This is a high impedance node and the FB resistors should be as close to pin as possible. The VCC2P5 node is very sensitive to noise and runs along the BGATE trace.
    3. The VCAP current sense trace shares the same trace to CAPFB. These two traces should be separated for accurate current sense measurements. 
    4. There should be a short path from the VOUTSP and VOUTSN traces to the input current sense resistor. VOUTSP supplies the Iq current to the LTC3350. This trace should be much wider to prevent the IR drop from reaching current limit. 

    The register reading provided shows that power returned, charge disabled for cap measurement, shunting, step down mode, 3 caps near 0V and 1 cap near 1.1V. These are odd reading which might have been caused by noise coupling into the VCC2P5 cap. If the trace to R59 is cut close to C59, does the part operate any better. Below is a link to the demo board design files. If a new layout is needed, please use this layout for a reference and also refer to the PCB Layout Considerations section on page 30 of the LTC3350 datasheet as well. .  https://www.analog.com/media/en/evaluation-documentation/evaluation-design-files/DC1937B.zip

  • Thank you for your swift response Marty!

    Shunt regulator and layout changes will be made in rev 2.

     

    The screenshots requested are below before changes were made, as well as some after the following changes were made.

    Adding 100nf cap to PFI line.

    Vc cap was replaced with 1nf

    Trace to R59 has been cut

     

    The caps were also charged externally at a constant current of 1.5A to a total across the stack of 2.5v. The external charge was then removed and the stackup was measured. The caps were observed to be discharging.

    Sw line 

    PFI 

    2.5v line 

    CH1 PFO, CH2 VIN 100us

    CH1 PFO, CH2 VIN  500us

    CH1 R59 Trace, CH2 BGATE 

    Their does appear to be some noise on R59 coupled from the BGATE trace.

    Changes were made to the board here

    Trace has now been cut R59

    Vc cap was replaced with 1nf

    Adding 100nf cap to PFI line.

    CH1 PFI, CH2 VIN.  After adding 100nf cap to PFI line.

    CH1 PFI, CH2 VIN, CH3 TGATE,