Dead chip or bad design? (LT8710 not starting up)

Hi All,

Looking for some help as I've designed a SEPIC converter around the LT8710EFE to take a 4S Lipo battery ~14.5V and output 28V at up to 100W, however providing the input power it does not generate the expected output.

I've designed and simulated this circuit on LTSpice (can someone advise on how to attach a model here?) based off the example model provided by LT/AD here: (LT8710 Datasheet and Product Info | Analog Devices) 

However, when applying Vin to the real circuit there are a few strange things:

1. Without the En/FBin pin above the UVLO threshold (1.3V),
   1. the FBX pin is ~0.5V, the Csp is 1.73V, and the Vc pin is ~0.7V, all of which should be zero (per LTspice)
   2. The IntVcc is near zero (~20mV) when it should be 5.1V (per the LTspice simulation)
      1. this also means the Flag and Mode pins are not at their expected 5.1V
   3. the Imon pin is at zero where the LTspice simulation has this pin at 0.616V
2. When the En/FBin pin is brought above the UVLO threshold (1.7V)
   1. the IntVcc does generate the expected 6.3V, bringing Mode up with it
      1. but Flag remains low
   2. the Vc pin rises to 1.29V,
      1. Per the state diagram (figure 2, page 11 of the DS) within the "Active mode" state the Vc pin should be pulled low
      2. Per the LTSpice simulation, the Vc pin is low until the EN pin goes above 1.3V
      3. 1.29V on the Vc pin is what's expected once the regulator reaches steady-state output
   3. the SS pin ramps to 2.53V, but from LTspice this should be closer to 6.3V
   4. The Csp rises further to 2.62V which is still greater than the 0V LTspice forecasts
      1. additionally, even when the simulation has the device switching as expected, the maximum this pin should reach is 20mV
   5. The BIAS pin (connected to Vout) rises to 1.732V, well short of the expected 28V.

(Apologies for the slightly messy layout, I was cramming a lot onto one sheet)

Just in case the image is too hard to read:

• L = Wurth Elektronik 74485540220, Dual inductor (1:1), 2.2uH each
• "C1" (bw Inductors) = 2x10uF Ceramic 50V X7S 1206
• MN = Onsemi FDMS86500DC, 60V, 108A (2.3mR) N-Ch MOSFET
• MP = Vishay Si7461DP-T1-E3, 60V, 8.6A (14.5mR) P-Ch MOSFET
• Rsense1 = 1mR, 0603, 1%, 1/10W
• Rsense2 = 8mR, 2512, 1%, 5W
• Cin = ~178uF, Ceramic - for this application Electrolytics are not allowed
• Cout = 60uF, Ceramic
• Rfbx = 320k
• Rrt = 88.7k
• Cimon = 47nF
• Css = 440nF** (I put another 220uF on top of the one PCB after realizing I was under the 5xCimon requirement)
• Vc network: (18kR + 3.3nF)//100pF
• Rsense filters: 5.1R/15nF
• EN/FBin UVLO voltage divider: 13.3kR + 10kR
• There are also a few zero-ohm resistors for testing, along with an op-amp on Imon to scale/buffer the current monitoring for uC reading
• an LC filter on the output buffers the regulator from some harsh switching when operational
• The EN/FBin pin is controlled through a P-ch MOSFET driven by the uC with 3V3 when required, otherwise is naturally disabled (P-Ch shorts pin to ground, gate is pull down). 

Any assistance/advice on this matter would be greatly appreciated