Noise -> 100uV

Hi.   I don't think you will be happy with my response, but here it is anyway.  From my observation, higher output current can increase noise just at higher frequencies but just over a relatively small range.  Your ADJ pin resistor divider will tend to "gain-up" the noise and the feedforward capacitor would defeat that increase, but you still won't get the noise below the 100uVRMS that is specified.   I would not expect the resistor noise to contribute in this case.  Most customers don't like the LC solution and that must be why low noise LDOs are so popular.  The resistor in series with IN will dissipate power which can be useful to cool the LDO, but the bypass capacitor at the IN pin should negate the effect of the Rseries on stability.   We have an LT308X line of LDOs that are 40uVRMS noise and can support arbitrarily high IN an OUT voltages since there is no ground pin.   

Hi,
you should have a look at datasheet page 7, the diagram "Input Ripple Rejection" over frequency.
So I would recommend a line filter in front of any regulator that has low PSRR at higher frequencies.

Hi, thank you very much for your suggestion, I like it !    I extensively studied the several datasheets, and I decided to go for the LT3081: very low noise (27uV), still floating architecture, higher bias current (50uA vs 10uA), which I believe makes things little bit easier when it comes to layout. At the expense of higher dropout (which for me is not an issue), and worse PSRR at higher frequencies.

So, the updated design is the one you can see in the picture below. May I take the opportunity of your patience for a couple of additional questions ?:

- I understand that all max voltage specs are related to Vout (40Volt max input vs. Vout). So, the input voltage can be any, provided that the difference with Vout is lower than 40V. In my case Vin should be 42 Volt, according to my simulations. My paranoid mind is asking one question: what happens at startup or shutdown ? Is there any risk to violate the Max (Vin - Vout) = 40 Volt rule ? I mean, will Vout 'follow' quickly Vin at startup, and the same at shutdown ? Or will be there some mS when the rule is not satisfied ? Fyi, my load is 6mA (I added 16K resistor, just to add 2mA). Cables to the load some 40cm long. Load with 1uF coupling cap.

- In order to mitigate the not ideal high frequency PSRR, I think to deploy a low pass filter, Fc about 5Khz, based on 2Ohm resistor and 15 uF. Thanks to Alexxx advice also. Are you happy about this, I mean, no impacts on stability ?

Thanks again !!

Cheers

Matteo

Thanks Alexxx, good point ! I updated my design accordingly, see my reply below. A good day ! Matteo

Hi.  Make sure you clamp SET and OUT to IN with zeners as I show in the image below that is a reference design of a negative LT3091 HV.  The positive is actually easier since there is no GND pin.  Make sure the clamps can tolerate start up and a fault like a shorted output - the series R may help for that.  You should be able to check stability by using LTspice and a load transient test.    

Thank you very much ! I'm editing the previous answer, as I'd like to share the outcome - calculated through LT Spice - might be interesting. Any comment is more than welcome on this !  Please find the circuit I've developed, at the end of this reply, below. (please note the 36V zeners as you suggested). 

- The LT3081 was not completely happy / stable with R3 = R8 greater than 1 Ohm. Regular 0.1V peaks over the regulated voltage of 32V, each every 0.077mS (i.e. about 13Hz). Hence, I reduced those resistors to 0.15 Ohm.

-  On the first plot below: green line is the filtered DC at the input of LT3081. Blue line is the output from LT3081 (32V). Red line is the difference between input and output. I simulated switch on, and switch off after 1s. We can see that this difference (red) almost never reaches 36V, just a short interval at the startup. So, I understand the zeners are engaged just at the very initial milliseconds.  On the second plot the FFT (output) is reported: nice and clean as it should be (it's calculated over the time when the situation is stable, I removed startup and shutdown).

- I then simulated short circuits, and following stability, by making my load switching from 0.006 A (my normal load) to 100.000 A at 0.5Seconds, and back to 0.006A at 1.2 Sec. Seems ok to me (zeners engaging just at each switch):

- Same (nice) situation for variations of input voltage of -18% -> +20%. Output voltage steady at 32V.  

- Further increasing the input voltage - to 80V for example (which is +90% of initial value), the zeners contribute to 'bring up' the output voltage / SET voltage, in order to keep the LT3081 in safe area, as it can be seen in the first plot below: (purple reports the current through zener D1). Of course the output voltage from the regulator is 'dirty' in this case, more and more similar to the input voltage, as the Vin itself increases. See  the new FFT below:

Thanks again, for your comments in case

Cheers

Matteo