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LTC7060 BGVcc Current Draw Clarification

Category: Datasheet/Specs
Product Number: LTC7060

Hello I am looking through the LT7060 datasheet and found the plot of Switching Supply Current vs Load Capacitance.


When I model this in my dc-dc converter in LTspice with a battery simulated as a 10mF capacitor, I am seeing BGVcc pulsed currents of ~2-3A, BST peak currents of ~16A, and TG currents of ~3A. Is this expected and realistic behavior due to my high capacitance at the load and if so, does analog devices offer any type of LDO that can supply this current?

Thank you,
Michael

  • I do notice that for the reference design included in the LT7872 LTspice example circuit which includes LTC7060s whose BGVcc is powered from the DRVcc pin, 1.6A pulses are drawn from the LT7872's DRVcc pin, which is rated for only 150mA on the datasheet.

  • Hello, I have adjust BST's input source to a lower voltage, and am seeing only 3-4A of peak pulsed current at all pins mentioned previously..

  • Hello Michael,

    The maximum current rating for the LTC7872’s DRVCC pin is 150mA DC. Per the simulation, the DRVCC current is 28.5mA DC. Therefore, it is well within the rating. The DRVCC current can be estimated from the switching supply current vs load capacitance curve from your post. It can also be calculated with the formula below:

    IGATECHG = f * (QT + QB) * N

    Where f = switching frequency

    QT = total gate charge for the top MOSFET(s) per phase

    QB = total gate charge for the bottom MOSFET(s) per phase

    N = # of phases

     

    The DRVCC and gate drive current noise is due to the following:

    • The noise on the LTC7872 DRVCC pin’s current is due to the charging of the bottom MOSFET's gate to source capacitance and the refresh of the boost capacitor.
    • The noise on the LTC7060 BST pin’s current is due to the charging of the top MOSFET's gate to source capacitance.
    • The noise on the LTC7060 TG pin’s current is due to the charging and discharging of the top MOSFET’s gate to source capacitance.

    The actual noise on the PCB will be much smaller than in the simulation due to the trace impedance and the ESR/ESL of the boost capacitor, BGVcc capacitor and DRVCC capacitor.

     

    Best regards,

    Mike

  • Thank you for the clear answer Mike, I appreciate it. I will include some high frequency bypass capacitors at the LDO output as a precaution.

    Regards,
    Michael