LTC4364-2 MOSFET M1 Failure

Q1 needs the Safe Operating Area (SOA) performance to survive 4 situations:

1. Start-up. Inrush current is controlled by slowly slewing Q1. Ease SOA stress using ENOUT to keep Load off until Cout is charged.
2. Hard Short. (Current limit folded back to 50%)
3. Soft Short. (100% Current Limit)
4. Input Surge (Vin rises to max Vin during full load).

There are previous posts detailing the calculations for these 4 points.
Size the TMR cap to stay within the FET's SOA. 
You can use LTspice to see the exact timeout in situations 2-4.

I suspect the FET fails during start-up. Use the ENOUT feature.

When I observed the MOSFET failure, the PCB area around the MOSFET was black and seems to be delaminated due to heat. I think this kind of damage will not happen in an instant. It should be because of a prolonged stress. Hence, I cannot assume that the failure is at the start up.

Also, we are testing with a resistive load and there is no Cout.

So, what could be the possible reason for the failure?

Could you please help us find the root cause.

Harish_I_I said:

When I observed the MOSFET failure, the PCB area around the MOSFET was black and seems to be delaminated due to heat. I think this kind of damage will not happen in an instant. It should be because of a prolonged stress. Hence, I cannot assume that the failure is at the start up.

Startup is a common cause of failure, since there is VDS across the FET while the output cap charges and the load draws current. I*V=P.

Harish_I_I said:

Also, we are testing with a resistive load and there is no Cout.

I see 22uF of output cap in your schematic. Of course the resistor also contributes to stress during startup.

Harish_I_I said:

So, what could be the possible reason for the failure?

It's one of the 4 situations I posted.
I suggest plotting these points on the FET's SOA graph.
The FET needs to be able to survive each situation, and if it does, the FET should not fail.