EN/UVLO pin condition define

This is an hysteresis to avoid glitches and such.
Therefore when booting up (Ven rising) you need to get up to 1.24 V before exiting the UVLO condition.
However, once enabled, you will only enter UVLO once the voltage on EN fall below 0.6V.

Hence, if Ven is a bit noisy, you have some margin to avoid rebooting your system.

Thank you ,

Could you also tell me , what is "Enable Hysteresis" , what is the different between shutdown/enable threshold ?

So, in the rest of the datasheet, the falling UVLO level mentioned is 1.18-something V (see figure 23).
Hence the 55mV of hysteresis (1.239V-0.055 = 1.184V) which would be the difference between the level to exit UVLO (rising) and to go back into UVLO (falling).

Hence the question of the 0.6V of your extract...

In my opinion, either there is a UVLO level (below 1.184) and a SHUTDOWN level (below 0.6) or the 0.6V is a mistake in the datasheet.

Hi ElfaSys

The definition of shutown on LT8292 is also confused me.

I can't see the same define in other chip , ex. LT8210 ( below pic)

Can you help to check, what is  the defintion of shutdown (0.6V) in LT8292.

thank you

www.analog.com/.../lt8210-1.pdf

Hi dimitrychen,

You have the information on page 25 of the datasheet (for the LT8292):

So, below 0.6V nothing happen, at all.
Over 0.6 but under UVLO, you have bandgaps and internal stuff starting but no switching.
Outside UVLO, the circuit works nominally.