Hi,
I got some questions about ADP7118.
In the datasheet for ADP7118 the noise reduction network consists of a capacitor with the positive terminal connected to Vout and the negative terminal connected to a resistor which is connected to ADJ pin of the LDO. However in the evaluation board the noise reduction network the capacitor and resistor has switched places. In the schematic for the evaluation board the resistor is conneted to Vout followed by an unpolarized capacitor which in turn is connected to the ADJ pin. So I'm wondering which is the correct noise reduction network for ADP7118?
Also I'm looking for guidance in selecting the sane capacitor and resistor values for the voltage divider and noise reduction network. The goal is to output 8V. So the 5V output version of ADP7118 was selected. The voltage divider nework of R1 and R2 with a value of 60,4k for R1 and 100k for R2 was selected which yields a theoretical value of 8.02V which is acceptable. Then the resistor for the noise reduction network (Rnr) was selected to be 10% of R2 in accordance with the datasheet (1-10% of R2 was recommended as I read it) so 10k was selected. Now for capacitor of the noise reduction network I selected 2.2uF which if my calculations is correct is the reactance of 50,4k (R1-Rnr) and frequency of 1,44Hz (according to the datasheet should be set from 1-50Hz).
I'm just a beginner in electronics and my calculations for the capacitor in the noise reduction network is the trickiest part for me. Hope it makes sense to you and please correct me where I'm wrong. Would like to get the values correct before sending the PCB to manufacturing and sourcing the BOM.
Thanks in advance!