Floating the LT4363 for operation at 144Vdc

Instead of floating the LT4363, there's LTC4366 floating surge stopper. But you shouldn't need a floating controller unless the nominal voltage is high.
If you want something like the LTC7860 but NFET based, go with the LTC7862.

So if your surge is 144V, what is the typical/nominal input voltage?
What is the max load current?

DaveAtIdeon said:

I'm aware that there will be significant stresses on the power fet during the regulated period of the surge - so I'm planning on having 2-3 fets with a combined gate charge of around that of the one supplied in the datasheet

You can't rely on the FETs sharing SOA when you parallel them, due to Vgs(th) mismatch.
You must assume the worst case: 1 FET takes all the stress.

Thanks Ashapiro , But the LTC4366 isn't designed for short circuit protection, it's designed for over voltage - which I don't technically require (though I've done it here more so to test it's behaviour). What I care most about is protecting upstream parts of my system from downstream short circuits or over current. So I need the current monitoring a cut-off. 

Yes, using FETs to share stress is risky, which is why I'll be doing everything I can to derate against the events and give them lots of copper to sink to. I'd be happy to shorten the timer even more than the 10msec and, since I'll have a micro in the loop. I can always use the latching form of the IC to extend the cool down period between retries if that's needed. Though initially, I was hoping to use it more to disable only after a certain number of retries. 

Hmm, we don't have any hotswaps or surge stoppers with active current limiting than can go up to 144Vdc.
I think the +100V offset is a problem for the current sensing [50mV differential signal], and I'm not sure what happens if you float the chip.

DaveAtIdeon said:

Yes, using FETs to share stress is risky, which is why I'll be doing everything I can to derate against the events and give them lots of copper to sink to. I'd be happy to shorten the timer even more than the 10msec and, since I'll have a micro in the loop.

Heatsinking only helps for t>10ms, due to thermal impedance between the case and heatsink.
The FET is on its own for short SOA events.

Thanks Ashapiro, I'm just seeing this now.

So LTC7862 does work like this, but it's pmos and is also switching mode for regulating through the short - two things I'd like to avoid, since I care more about normal operation conduction losses (this is part of a daisy chain system where this protects against a fault in the next system down the line which also has one of these, and so on) and only care for a clean cut-off during a fault. There is an nmos surge stopper that shows floating operation, the LT4380, but the application circuit doesn't go up high enough and I liked the specific design of this one a little better for my application, which is why I choose it. I took inspiration from both these datasheets as well as the LTC7862 circuit we've currently implemented (which is working) to create the one above. It appears to work just fine in simulation and the logic of it feels sound to me: during a short, the floating ground will follow the shorted output so that the gate voltage is never too high of a differential.

So, outside of the momentary shock to the fets from trying to regulate the short circuit, I don't see anything that could be a miss - other than some concerns around the floating part of the circuit keeping within a happy gate voltage level - again it works fine in simulation, but I'm really hoping I didn't miss something. 

I'm fairly certain this sort of floating operation is something that's been designed for others in the past, based upon very old conversations I had with AFEs back in the LT days, which is why I'm hoping there's someone there with experience in this that could point out anything I'm missing or a better way of doing it.

As for the FETs and sinking heat into the PCB, yes I should have been more clear. I realize that junction/case transfer is the limiter here and it's unlikely that extra copper will aid much over such a short pulse. But it should help to cool it off quickly for when the next turn-on happens, assuming a short still exists. So it's obviously going to be something I very carefully design for. 

Anyway, thanks for your input! 

Cheers,

Dave

DaveAtIdeon said:

So LTC7862 does work like this, but it's pmos and is also switching mode for regulating through the short

I think you are confusing the parts.

The LTC7862 uses NMOS for both the control and synchronous FET.


The LTC7860 uses a PMOS control FET and is asynchronous.

DaveAtIdeon said:

So LTC7862 does work like this, but it's pmos and is also switching mode for regulating through the short

I think you are confusing the parts.

The LTC7862 uses NMOS for both the control and synchronous FET.


The LTC7860 uses a PMOS control FET and is asynchronous.

Yes, it's the LTC7860 that I'm referring to, not the LTC7862 - sorry for the confusion. I've had too many of these datasheets scattered across my desktop for too long trying to piece this together. The current design is based on the LTC7860. But it requires PMOS fets with large RDons and large caps and inductors all of which I'm trying to design out with this design. If the above circuit works, it will be vastly smaller, much cheaper, and much lower loss during operation. It would also have an impact from the supply chain side, as there are much fewer pmos that can fit the bill for what we're trying to do (the current fet is currently not stocked by suppliers for example). Thus, where I'm at.