I am having an inrush issue with a design using the LTC4364 and FDMC86260. Initial power on has a negligible inrush but subsequent power cycles have a failing inrush (~15A). The inrush is aligned with the rise of the input voltage; not the controlled turn on of the FETs (~30ms after input power applied).
I suspect that the 4V threshold of my FETs are too low and residual voltage on HGATE is allowing Q4 to be partially turned on. If I probe HGATE directly with an o-scope probe, the issue goes away. I suspect the 1M load of the probe drains off the residual voltage.
Is there a way to prevent (or drain) the residual voltage on HGATE? Is there a recommended minimum Vgs threshold for the FET selection? Operational Vin is 15V to 40V.
In the image below... CH1 (yellow) in the input voltage. CH2 (green) is the voltage between Q4 and R43.

Thanks for the help.