MAX16127 OVSET/UVSET rising & falling edge dependencies, Avoid gate absolute maximum limits

Hi Santu17,

Please see below response to your inquiries.

Question #1. In MAX16127 EVKIT, there's 0.6V & 1.4V difference in rising & falling edge w.r.t UVSET & OVSET respectively. What are the parameters influencing this variation? Hysterisis of 0.05*1,225V & schottky diode of 0.3V?

When utilizing the EVKit setup, hysteresis is present due to the presence of large capacitor C4 (330uF) at the output.

For evaluation purposes, removing this capacitor would give significant reduction in observed hysteresis.

Question #2. If we're planning to use the MAX16127 over 35V(Our req: max.38V) then what are you recommendation? I have below implementation in mind, let me know an optimal solution:
a. if we provide low tolerance 38V zener diode at the input so that we can avoid gate voltage exceeding 45V or
b. provide low tolerance 45V zener diode at the gate pin w.r.t ground?

I would recommend option A for this purpose.

Question #3. 

What does -60V to +90V full featured solution? Only transients support? Also, it'd be helpful if you could explain the importance of 75V zener diode at D1 in evaluation schematics. 

Full featured solution exercise all the features of MAX16126/7 and tolerating -60V to 90V.

From EVKit schematic, D1 helps to clamp positive voltage variations, in this case D1 is rated up to 75V.

Question#4. What are the consequences if we use OVSET resistors connect to TERM pin (Just like MAX16126) instead of recommendation for MAX16127? Will it fail to operate in voltage limiter mode?

Yes, the configuration should be in a close loop mode operation and it functionally needs the OUT node.

Question#5. Do you have any new solution which is operable above 35V in normal operation?

Here are some ADI offerings with voltage input range greater than 35V are MAX16128/29 and MAX17527.

Thanks,

Chris

1. If we don't consider bulk capacitors then can you tell approx. values of OVSET_rising & falling edge?

2,3. In evaluation board, it's mentioned that we can go beyond absolute max.ratings! The SRC & gate voltages have a max.rating of 45V then how the circuit is going to operate ~75V?

5. MAX16128/29 also has similar absolute maximum ratings as MAX16126/7, how is that supposed to help with operation voltage >35V? 

6. Discrepancies in resistor selection formulas of datasheet & evaluation board! In datasheet, there's a consideration of hysteresis(0.05*Vth) but doesn't consider the impact of term-on resistance.... In evaluation board, it's vice-versa! Leading to different values of OVSET & UVSET. Which formula is more accurate?

2,3.  In evaluation board, it's mentioned that we can go beyond absolute max.ratings! The SRC & gate voltages have a max.rating of 45V then how the circuit is going to operate ~75V?

Please disregard my previous response. The D1 inclusion was placed to add protection for positive voltage transients, and this is not to extend the normal operating voltage. To extend the operating voltage above 30V, a Zener diode clamp can be added GATE-to-SRC of the MOSFETs to limit the GATE voltage.

5. MAX16128/29 also has similar absolute maximum ratings as MAX16126/7, how is that supposed to help with operation voltage >35V? 

Placing zener diode clamp D3 Gate-to-SRC would help in increasing input voltage operating range up to 45V.

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I'll get back on other items on this inquiry as these need further validation.

Also, can you explain the reason for a large 330uF capacitor at the output(C4/C10).

If we're designing a custom board with connected power supplies on the board itself then we don't have to provide such large capacitance right? The large capacitance is provided to reduce ripple during board to board transition with wire right?

1. If we don't consider bulk capacitors then can you tell approx. values of OVSET_rising & falling edge? 

Measured values with Vout capacitor.

UV Rising 9.09V

UV Falling 8.2V

OV Rising: 31.9V

OV Falling: 31.5V

If we're designing a custom board with connected power supplies on the board itself then we don't have to provide such large capacitance right? The large capacitance is provided to reduce ripple during board to board transition with wire right?

Load dump circuit output capacitor tends to filter out high-frequency noise and stabilize the output voltage specially during sudden changes in the load current or input voltage.

1. If we don't consider bulk capacitors then can you tell approx. values of OVSET_rising & falling edge? 

Measured values with Vout capacitor.

UV Rising 9.09V

UV Falling 8.2V

OV Rising: 31.9V

OV Falling: 31.5V

If we're designing a custom board with connected power supplies on the board itself then we don't have to provide such large capacitance right? The large capacitance is provided to reduce ripple during board to board transition with wire right?

Load dump circuit output capacitor tends to filter out high-frequency noise and stabilize the output voltage specially during sudden changes in the load current or input voltage.