Was intermittent at first, now all the time - when the CHARGE pin is low, voltage on the UVLO and OVLO pins, both 1 and 2, nearly equal the source voltage of the resistors that feed them, but when CHARGE is driven high, then their voltages are correct (Vsource - 50uA x R). It is as if the 50uA current sources are turned off when the CHARGE pin is off (logic low).
My circuit is pretty close to the dev board DC1322, set up in regulation mode. Vcc is supplied by an LT3010 just like on the dev board. Everything designed per the datasheet using parts recommended by the datasheet or what's used on the dev board. Used good layout practices.
I need to know if this is a known failure mode, and what might cause it. Initially to make sure I need to change the chip on my prototype board, but also to understand if there's something to avoid or do to avoid this failure in production (e.g. extra ESD protection device? some known design practice?)
Thanks!