LTC4368 - SHDN goes low and output switched on

Kariba said:

I would expect that the gate will be pull to low and the output voltage decrease or will be hold on around 2V. 

I think this is happening, but just at a slower pace than you expect.
When you pull SHDN# low, NFETs are discharged with IGATE(SLOW), which is 90uA typical.
Once GATE falls below the NFET's threshold voltage, OUT should drop.
Add a bleeder resistor to the output to discharge COUT once NFETs turn off.

Hi Ashapiro

thank you for your reply. 

Ashapiro said:

I think this is happening, but just at a slower pace than you expect.

I would expected around t = Q/I = C*U / I = ~3nF * 2V / 90uA = 100us. This correct behaviour you can see on the first image on the second negative edge of SHDN (EN). 

Ashapiro said:

When you pull SHDN# low, NFETs are discharged with IGATE(SLOW), which is 90uA typical.
Once GATE falls below the NFET's threshold voltage, OUT should drop.

But the opposite case happened. SHDN = low -> Gate goes to high 

Ashapiro said:

Add a bleeder resistor to the output to discharge COUT once NFETs turn off.

Yes. Good idea.

Best regards

Kalle

Kariba said:

But the opposite case happened. SHDN = low -> Gate goes to high

I suspect the issue is that the SHDN# pin is inside the UV-OV divider.
If you plan to apply a signal to the SHDN# pin, use the circuit below:

Utilize the FAULT# pin to help with debugging.

Hi,

Ashapiro said:

I suspect the issue is that the SHDN# pin is inside the UV-OV divider.

sorry I forgot to mentioned it, it was only indicated in the circuit diagram above. The SHDN pin is directly connected to a micro Controller. 

Ashapiro said:

Utilize the FAULT# pin to help with debugging.

Hm. This I could try. 

Best regards

Ashapiro 

Hi,

I measured the FAULT signal. If you can see the Fault signal is set to low, but the gate voltage rised up ? 

When a fault condition was detected the gate current is 60mA ? When the SHDN is set to low level the gate current changed from 60mA to 90uA ? And when this happen the gate voltage increase to 5V. Do you have an explanation for it ?  

Best regards

Kalle

That's interesting.
What was the test condition? (that triggered the FAULT# to pull down)
Was VIN stepped outside the UV-OV window, or perhaps a load step that tripped the circuit breaker?
I can try replicate on my end if I get more details.

@ashapiro

It was an over-current condition and the VIN window is fine. 

Would be nice if you can try it. 

Best regards

Kalle 

I tested on the bench and saw similar behavior.
Looking at the SHDN# pin description, we find that toggling it can clear overcurrent faults even if latch-off behavior is set.


Here's a sim confirming behavior:


Have a good holiday,
-Aaron

Hi Aaron,

thank you for your reply. I hope you had a good holiday time, too ?

Your simulation do not show the same behavior. The same behavior would be:

At 0.6s when the SHDN signal goes low, the gate voltage go high, too. But in your case the gate signal goes high in the same time the SHDN signal goes high.

Best regards

Kalle. 

I tried replicating the issue on a demoboard.
I set the controller to latch-off, and triggered an overcurrent fault so GATE would be low.
Then, I toggled SHDN#.
The falling edge of SHDN# does not make GATE go high, only the rising edge does.

Maybe you need to debounce: Try a little RC between the micro's I/O pin and SHDN#.