Category: Hardware
Product Number: LT4293
Hi,
I want to ask for a little more details regarding the LAB_TEST_VOUT- pin on the DC2911A demo board. I see that it's intended for lab testing with a resistive load. Just want to get a good understanding of what are the risks if I apply a resistive load across the VOUT+ and VOUT- instead of using the LAB_TEST_VOUT- pin? Want to confirm if the LAB_TEST_PIN- is to protect instances with transients when the load is shorted while PWRGD is high enabling the LT4321? So would the risk here be potentially damaging the LT4293 device and possibly the Q1 FET?
Thanks for the help and insights.
Jerry