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LT4293 Recommended for New Designs
The LT4293 is an LTPoE++/IEEE 802.3af/at/bt-compliant powered device (PD) interface controller. The T2P output distinguishes between LTPoE++ and IEEE 802...
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LT4293 on Analog.com

LT4321 Recommended for New Designs
The LT4321 is a dual ideal diode bridge controller that enables a Power over Ethernet (PoE) powered device (PD) to receive power in either voltage polarity...
LT4321 on Analog.com

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LT4293 Demo Board (DC2911A)  LAB_TEST_VOUT- pin

		
	
				

			

									
					    jleung
					
							

            
            			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Oct 24, 2023 
				
			
			
		
    
		
		                    	    
    
        	    
    Thread Summary
    
                The user inquired about the risks of applying a resistive load directly across VOUT+ and VOUT- on the DC2911A demo board instead of using the LAB_TEST_VOUT- pin. The final answer explains that doing so can increase MOSFET stress during inrush, potentially causing component damage and non-IEEE compliant behavior. The LAB_TEST_VOUT- pin is a low-side switch that closes after inrush, simplifying evaluation with resistive loads. Capacitive loading of LAB_TEST_VOUT- should be avoided to prevent stressing Q11.
                        	    
    
                
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    Category: Hardware
    
    		        		            		    
    Product Number:  LT4293 
    
    		        		    		    
    
		    		    
		    			
    
			    
    Hi,
    

    I want to ask for a little more details regarding the LAB_TEST_VOUT- pin on the DC2911A demo board.  I see that it's intended for lab testing with a resistive load.  Just want to get a good understanding of what are the risks if I apply a resistive load across the VOUT+ and VOUT- instead of using the LAB_TEST_VOUT- pin?  Want to confirm if the LAB_TEST_PIN-  is to protect instances with transients when the load is shorted while PWRGD is high enabling the LT4321? So would the risk here be potentially damaging the LT4293 device and possibly the Q1 FET? 
    

     
    

    

    Thanks for the help and insights.
    

    Jerry
    
			
    
			
									
		                             
                        

    
    
                                            
                 PoE Powered Device (PD)
                
                                                    
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                 Power Monitor  Control  and Protection
                
                                                    
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      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Jan 7, 2026 3:19 PM
            
            
						
			            		
      
		
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      Hi Jerry,
      

      Due to an issue with EZ I did not receive notifications for this post. My apologies. I understand this reply is likely too late to be useful for you. In case anyone else has a similar request, I will answer your question.
      

      Applying a resistive load across VOUT+ to VOUT- increases hotswap MOSFET stresses during inrush up to component damage and may cause non-IEEE compliant behavior. The LT4293 controls the Q1 gate voltage to set the current flowing into C4. Any resistance at VOUT+ to VOUT- will present an additional current. LAB_TEST_VOUT- is a low-side switch that closes after inrush has completed, simplifying evaluation with resistive or uncontrolled loads. You should not capacitively load LAB_TEST_VOUT- as that would stress Q11.
      

      Best Regards,
      

      Eric 
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
				
						
				
				
				
		
		
      
			
		
      
	
      

      

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