I am not sure if this is the place to request help as this relates to a linear technology device, but if there is better place please advise, thanks.
The LTC4444 does not handle a DC high signal to the top gate input. With the bottom BINP at GND and the top TINP set to VCC at 9V, the top NMOS quickly gets permanently set high (damaged). In my case the load is 14 Ohms with VIN of 28VDC (2A load). I tried applying a decreasing TTL signal to the TINP input with the BINP at GND and found at 10 Hz 50% DC the top NMOS output can hold the 28V at 2A for no longer than 8ms after which it drops to 8V every cycle. I am using the typical circuit on page one of the LTC4444 datasheet.
A similar device the LTC7066 does not have this problem. Using the typical circuit on page one of datasheet for that device, when I apply a DC signal to the top TOPIN pin the top NMOS can hold 2A load indefinitely.
These devices should operate very similar to each other. Does the LTC4444 not allow DC signals on the top & bottom inputs? There is nothing in the datasheet warning of this.
Circuit components used in the LTC4444:
Boost diode D2 is mfg V2PM10L-M3/H. 550mVf @ 1A; 100V
Boost capacitor C5 is mfg CGA4J1X8L1H474K125AC. 0.47uF 50V
Decoupling capacitor C6 is mfg CGA4J1X8L1H105K125AC. 1uF 50V
NMOS Q5 & Q6 mfg NVD5C478NLT4G. 14A 40V
