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LTC4359 toggle SHDN pin with FPGA

Category: Hardware
Product Number: LTC4359

Hi,

There's reason why not connected SHDN pin to FPGA as control?

In some reason when SHDN is toggling from FPGA this process damage the FPGA.

The SHDN connected to 3.3v FPGA bank trough pull down resistor (10 Kohm).

In the data sheet SHDN connected internally to current source from IN pin (24v in my case) - maybe this is the reason ?

Thanks.

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    •  Analog Employees 
    •  Super User 
    Aug 10, 2023 in reply to NC123 +1 verified
    the pull down is only to not leave LTC4359 float (on state) before FPGA wake up

    Thank you for clarifying.
    The 10k would draw 2.4mA, and given the 2.6uA internal pull-up, SHDN# wouldn't reach…

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  • There's reason why not connected SHDN pin to FPGA as control?
    The SHDN connected to 3.3v FPGA bank trough pull down resistor (10 Kohm).

    Are you using an I/O pin of the FPGA to pull-down SHDN# through a 10k?
    This way, the FPGA controls the LTC4359.
    Should be ok.

    In some reason when SHDN is toggling from FPGA this process damage the FPGA.
    In the data sheet SHDN connected internally to current source from IN pin (24v in my case) - maybe this is the reason ?

    The internal pull-up on SHDN# only has 2.6uA of drive.
    I don't think this would be enough to damage an ESD protection diode on the FPGA.

    You can clamp the voltage at the I/O pin with a zener.
    Look at the FPGA datasheet for the abs max voltage for an I/O pin.

    Hope this helps,
    -Aaron

  • I'm using FPGA to control SHDN pin with 0-3.3V - the pull down is only to not leave LTC4359 float (on state) before FPGA wake up.

  • the pull down is only to not leave LTC4359 float (on state) before FPGA wake up

    Thank you for clarifying.
    The 10k would draw 2.4mA, and given the 2.6uA internal pull-up, SHDN# wouldn't reach 24V.
    I measured SHDN# voltage on the LTC4359 demoboard (DC1502A), and the voltmeter's 10Meg input impedance is enough to load the internal pull-up, and VSHDN#=1.7V.

    If you want to decouple the FPGA from the LTC4359, you can interface with the SHDN# pin via a logic-level transistor.

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  • the pull down is only to not leave LTC4359 float (on state) before FPGA wake up

    Thank you for clarifying.
    The 10k would draw 2.4mA, and given the 2.6uA internal pull-up, SHDN# wouldn't reach 24V.
    I measured SHDN# voltage on the LTC4359 demoboard (DC1502A), and the voltmeter's 10Meg input impedance is enough to load the internal pull-up, and VSHDN#=1.7V.

    If you want to decouple the FPGA from the LTC4359, you can interface with the SHDN# pin via a logic-level transistor.

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