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What is the LT8490 / LT8705 Gate driver peak current limit?

Product Number: LT8490

Hello, I apologize for my long winded nature. I tend to be explorative during my board tuning sessions which makes me find nuances with devices. So here is a lot of background:

I have two mosfets in parallel for both high and low side switching, M1, M2, M3, and M4 in my 30A LT8490 charge controller system. System functions fine but I am tuning it and was inspecting my gate driver traces and got concerned about gate driver peak current. These are some hefty gates,

The gate capacity total for both mosfets is about 6.6nF, or about 50nC.
These gate traces are 20mil, 1oz copper. They are rated I believe for 1.5A with those specs? The switch node traces are also 20mil, that is important because those
My switching frequency is 151kHz and I measure my low side switch turn on and off around 20ns and my high side about 80ns. The 8490 is rated for 20 and so are my mosfets. So the high sides are switching a bit slow but totally acceptable at 80ns.


Following some simple equations: with t being rise time, not the period . Again, simple, not getting into miller effects or adding the capacitance of the copper regions and components and snubbers.
I = C * dV/dt , inputting the data above I get roughly the following data for the various mosfets':

low side M2 and M3: 2A peak current for dV of 6.35V on the gate, 20ns, 6.6nF

high side M1 and M4: 16.5A for 50V gate, 20ns, 6.6nF

M1 and M4 experience 80ns slew, not 20ns. Which makes sense if my traces are not able to handle 16.5A, they instead saturate (or dubbed inductive impedance if I am not mistaken) and limit the current until the gate is charged enough to not draw current that saturates the lines anymore; limited gate charge up.

So I thought to widen my traces a bit to permit such amps...

So, my question is, what is the peak current limit of the LT8490 / 8705 gate drivers? Should I leave it limited like this so its safe for the driver? It functions fine, and the 8490 IC does not get warm or hot, but I hesitated and wanted to ask before I widen my traces where I may find the driver pop under the 16.5A peak.

Before you might say, "nah its probably fine where you have it, go ahead", this becomes more important as I will be powering a motor at 75V with the 8705 (same as 8490 just without the solar brains). At 75V out, that gate will reach 81V (which 8705 is rated to reach for the gate drivers), making that mosfet gate peak current reach 26.4A for my mosfets. Must I limit it which will give me a slew rate >100ns to keep the peak down?

One thing to maybe consider is the gate resistance, which I have no clarity on the internet whether that resistance is always 'active' or if thats after some inrush moment (0ohms at t=0, then reaches gate resistance when lightly charged... I do not know). My gate resistance is 2.2Ohms. This would limit any current to about 2.5A @ 6v, and 22A @ 50V and 37A @ 81V. These resistance inrush current limits are higher than what the capacitance inrush currents will theoretically draw, so maybe gate resistance for my case is not relevant.

By the way, the average current at my switching frequency (which is the low end of what this device can do) is about 3mA for the low side to 6mA high side @ 50V, 12mA high side @ 81V gate. That seems low to me, or is that a lot for this gate driver? The gate driver is powered by INTVCC which is rated for about 100mA @ 6.35V. Doing some power conversion of V * I = V * I, solving for I gate driver with 50V for example, is 12.7mA. Adding the average gate currents during buck-boost switching all 4 switches, (8 mosfets), that gives an average current of 3+3+6+6 = 18mA. My INTVCC doesnt droop; the data sheet says INTVCC has a range of 90mA to 165mA. The 165mA provides up to 21mA average current limit to the sum of all my drivers... curious? The chip again does not get hot or warm.

I did experience difficulty with some buck-boost instability, shoot through in this system and it just begs the question if this is related? Either way writing all this makes me want to double my INTVCC caps. I'll do that anyways, feels wise even if its not related.

The only information I see for driver limits in the data sheets are ratings like, 3300pF gate capacitance provides 20ns rise and fall times with some dead time values in the 200ns range. I am double that capacitance but still get 20ns on my low sides. That's the only reference I have for 'limits'.

Thanks!

Parents
  • The limitation of the MOSFET gate drives should focus on slew rate. If the slew rate is too high, the MOSFET switching losses will be too high and the MOSFETs will get too hot. Do not try to limit the current to the MOSFET gates because you want to minimize the slew rate. For the same reason you want to choose FETs with as low of a gate capacitance as possible. Follow the DC2069A demoboard example for what is acceptable for MOSFET gate capacitance and also follow this demoboard for best layout.

  • I understand that a better slew rate is needed to reduce heat, but a high enough peak current might blow the gate drivers righ? Or are these gate driver ports able to be shorted and nothing will be damaged?

    Looking at the DC2069A I see them using a BSC010NE2LSI mosfet. That has a gate capacitance of 4200pF, and they use just one; no paralelling. Where I am running 6600pF max, more realistically 6000pF because I was using the high/worst-case ranges to get 6600pF..

    Are you suggesting that 4200pF is what this chip can handle safely? If so, I will stick with that.

    I'll do my best to bring down my gate capacitance but that will be very challenging to say the least. So if the limit is 4200pF I want to know, or can it go more and by how much? I will run shy of 'that' limit.

  • You will have functional issues long before you damage the IC with too much gate current. A gate capacitance of 6000pF is nearing the functional limit but that will need to be evaluated on the application. Also, even if the gate capacitance is acceptable, you will still need to evaluate the specific mosfet on the application because they all function different in practice.

Reply
  • You will have functional issues long before you damage the IC with too much gate current. A gate capacitance of 6000pF is nearing the functional limit but that will need to be evaluated on the application. Also, even if the gate capacitance is acceptable, you will still need to evaluate the specific mosfet on the application because they all function different in practice.

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  • Thank you!

    That's what I needed to know, even if not quantitatively. You suggest I am nearing the functional limit where it comes down to a specific mosfet's behavior. No fear of gate overcurrent yet.

    I'll still try to bring down capacitance, but I know what to do now with less fear of driver overcurrent on the 8490/8705.