I am working on an ADP5050 design and have noticed in simulation the voltage drop due to a 0.5A step load is quite bad. I'm in need of thoughts/comments on how/if I can improve this. I've run the design for a 1.0V output supply rail in LTSpice which is working well, but I'm struggling to reduce the stop load output undershoot when using a load of 0.5A. Because this is a 1.0V rail a noticeable voltage drop is a problem. I'm seeing a ~300mV drop when in discontinuous mode which is a problem for me.
Screenshot of my LTSpice sim.
Blue = inductor current
Green = output voltage
Teal = step load enable
Red = stepload "load" current
In continuous conduction mode this is much better, but I'm unsure how to improve this as I have to support a lighter load when powering up an FPGA with no bitstream. Does anyone have any advice? The green line "V(out)" shows the large dip due to a 0.5A step load.
Here is another screenshot showing the output voltage droop due to the step load.