LT1764A ramps up at startup

Did you consider using an output capacitor since this regulator is a feedback circuit. It might affect the stability of the circuit. This is discussed more on page 11 of the datasheet. Let me know if there any improvements.

Regards,

Nino

I have used ample output capacitance, turns out this is not the problem. 

I believe I have solved the issue, and the explanation is this:

Due to a faulty condition regarding the rest of the circuit, at startup (and after that), a small net load current was flowing into the regulator, instead of out of it. Since the regulator does not have the ability to sink current (unidirectional pass transistor), this incoming current was flowing to ground through the two feedback resistors, because the output pass transistor of the regulator was shut off. I don't have a block diagram of the regulator, but based on common topologies, I believe this is the case. This also explains why the ADJ pin followed the change in output voltage - it is high impedance so it sunk no considerable current (probably the + pin of the error amplifier).

This resulted in the output resting at a higher voltage (since the voltage source that created the sink current was about 15V). But, actually, the regulator was cut off, and no damage was done to it since the ADJ pin did not exceed the 7V limit specified in the datasheet, and the voltage difference to the error amplifier did not exceed 180mV (1.21V at the - input (internal ref), 1.39V from the external resistor divider).

I have used ample output capacitance, turns out this is not the problem. 

I believe I have solved the issue, and the explanation is this:

Due to a faulty condition regarding the rest of the circuit, at startup (and after that), a small net load current was flowing into the regulator, instead of out of it. Since the regulator does not have the ability to sink current (unidirectional pass transistor), this incoming current was flowing to ground through the two feedback resistors, because the output pass transistor of the regulator was shut off. I don't have a block diagram of the regulator, but based on common topologies, I believe this is the case. This also explains why the ADJ pin followed the change in output voltage - it is high impedance so it sunk no considerable current (probably the + pin of the error amplifier).

This resulted in the output resting at a higher voltage (since the voltage source that created the sink current was about 15V). But, actually, the regulator was cut off, and no damage was done to it since the ADJ pin did not exceed the 7V limit specified in the datasheet, and the voltage difference to the error amplifier did not exceed 180mV (1.21V at the - input (internal ref), 1.39V from the external resistor divider).