Post Go back to editing

# LTC4359 MOSFET becoming Damaged

Category: Hardware
Product Number: LTC4359

Hello, I am configuring two LTC4359s in a diode ORing configuration with prioritization set by an MCU.  I'm using two SIR680LDP-T1-RE3 as the switch FETs.  See one side of the circuit below.   I am running into a situation that Q1 becomes damaged.  When there is no load, it always switches fine without damage.  However, when I introduce a load and pull current through these FETs, then exercise the SHDN pin on the LTC4359 to switch it on/off, at some point Q1 becomes damaged.  Q2 does not become damaged.  I see from the datasheet that R5 is necessary to prevent parasitic oscillations, and I have it on there.  I am also looking at the gate of Q1 and don't see any oscillation there.

Is there anything else that I can look at?

Thank you!

## Top Replies

• I am encountering a situation where both input supplies are connected and I turn off one of the channels by switching that FET to ground.  But it seems like at that time, I see that the SHDN…
• How do you calculate the 46 ms for the 10 uF output capacitor to charge up?

*20uF output cap.
I used the equation on p11 in the datasheet to solve for inrush.
Then I applied the IINRUSH=…

Parents
• What is the output capacitance? I see at least 20uF.
• What kind of load is on the output? (Resistive, constant current e-load?)
• How much current does it draw?
• I have 20 uF of output capacitance.

When I put a constant current e-load, it blows out that FET everytime I pull greater than 20 mA.  When I put a resistive load, i can pull upwards of 6A and switch it a few times (at least more than 10).  But eventually the FET still ends up dead.

You need ~8 Ohms of RLOAD to draw 6A given your VIN range.
Given your CLOAD and CGATE, it can take a max of 46ms for the 20uF of output cap to charge up.
Inrush is 66mA max, which is <<6A ILOAD, so we can ignore the inrush current.

Plot 50V, 6A on FET's SOA graph.

However, the SOA graph is for constant VDS and ID.
In our situation, VDS ramps up from 0V to 50V, and ID ramps from 0A to 6A.
We translate to constant VDS and ID by taking an average. This gets us 25V, 3A.

Looking at this point, we are under the 10ms curve, but above the 100ms curve.
Our output takes 46ms to come up, so there is basically no margin.

I recommend choosing a FET with better SOA performance.
Notice that the SOA curves on your FET are totally straight and in parallel with each other.
This manufacturer likely did minimal SOA testing, and neglected the Spirito effect. (I'll let you look this up)

Hope this helps,
-Aaron

• Thats interesting.  How do you calculate the 46 ms for the 10 uF output capacitor to charge up?  If I reduce the output capacitor, does that increase my margin?  I will also have a look at different FETs.

• Additionally, am I reading the datasheet (page 3, "delta Vgate" gate drive parameter) correctly in the picture below that the gate drive voltage should be 12V when VIN is at 48V?  When my FETs are in the ON position, I am measuring Vgs on Q1 and it is only 3.5V (51.5-48V).  Is it supposed to be this low?

• It seems like it may be something besides the safe operating area, because I am using a significantly smaller 1.3A load (37 ohm) and it is still damaging that Q1 FET.  I am also monitoring the gate and source voltage and current through the FET and do not see anything coming in that seems to be damaging the device

• How do you calculate the 46 ms for the 10 uF output capacitor to charge up?

*20uF output cap.
I used the equation on p11 in the datasheet to solve for inrush.
Then I applied the IINRUSH=COUT*dv/dt and solved for dt.

Additionally, am I reading the datasheet (page 3, "delta Vgate" gate drive parameter) correctly in the picture below that the gate drive voltage should be 12V when VIN is at 48V?  When my FETs are in the ON position, I am measuring Vgs on Q1 and it is only 3.5V (51.5-48V).  Is it supposed to be this low?

VGS is only as high as it needs to be to regulate a 30mV drop.
At light loads, it doesn't need to fully enhance the FET.

It seems like it may be something besides the safe operating area, because I am using a significantly smaller 1.3A load (37 ohm) and it is still damaging that Q1 FET.  I am also monitoring the gate and source voltage and current through the FET and do not see anything coming in that seems to be damaging the device

The fact that the switch FET (Q1) is being damaged during start-up hints at an SOA issue.
I recommend using a different FET model with a good SOA graph. (must have Spirito region)
Also, if you wait until after the output cap is charged before you enable your load, RLOAD won't contribute to start-up stress.

-Aaron

• How do you calculate the 46 ms for the 10 uF output capacitor to charge up?

*20uF output cap.
I used the equation on p11 in the datasheet to solve for inrush.
Then I applied the IINRUSH=COUT*dv/dt and solved for dt.

Additionally, am I reading the datasheet (page 3, "delta Vgate" gate drive parameter) correctly in the picture below that the gate drive voltage should be 12V when VIN is at 48V?  When my FETs are in the ON position, I am measuring Vgs on Q1 and it is only 3.5V (51.5-48V).  Is it supposed to be this low?

VGS is only as high as it needs to be to regulate a 30mV drop.
At light loads, it doesn't need to fully enhance the FET.

It seems like it may be something besides the safe operating area, because I am using a significantly smaller 1.3A load (37 ohm) and it is still damaging that Q1 FET.  I am also monitoring the gate and source voltage and current through the FET and do not see anything coming in that seems to be damaging the device

The fact that the switch FET (Q1) is being damaged during start-up hints at an SOA issue.
I recommend using a different FET model with a good SOA graph. (must have Spirito region)
Also, if you wait until after the output cap is charged before you enable your load, RLOAD won't contribute to start-up stress.

-Aaron

Children
• Hello Aaron,

It seems like the FET failure may be related to the SOA and my electronic load.  It does not blow out when I use a significantly smaller load and I'm working on getting some FETs with better SOA operation.

But I did have another question regarding the shutdown function of the LT4359.  As you can see from my schematic, I have implemented an MCU controlled FET that shunts the SHDN pin to ground when I want to disable a particular input supply.  I am encountering a situation where both input supplies are connected and I turn off one of the channels by switching that FET to ground.  But it seems like at that time, I see that the SHDN on the channel I desire to keep on gets pulled low for about 4 ms (and even below ground to -6.6V) and turns off that side as well.  Since my MCU is powered downstream from these LTC4359 circuits, it resets my MCU and is problematic.

In the datasheet in figure 3a, the source of Q4 is tied to ground and the Vss of the LTC4359 is tied to ground through a 1k ohm resistor.  In my circuit, I have tied the source of my FET directly to ground along with my MCU ground so that they share the same ground reference and I thought this would address the comment on page 8 regarding figure 3a about there being glitches on SHDN during transients.  What is the purpose of this 1k resistor? Is the reasoning regarding tying the MCU ground to VSS on LTC4359 valid?

• I am encountering a situation where both input supplies are connected and I turn off one of the channels by switching that FET to ground.  But it seems like at that time, I see that the SHDN on the channel I desire to keep on gets pulled low for about 4 ms (and even below ground to -6.6V) and turns off that side as well.  Since my MCU is powered downstream from these LTC4359 circuits, it resets my MCU and is problematic.

1. Add enough output cap to reduce voltage droop during switchover, so uC doesn't turn off.
2. Have a separate diode-OR supplying the uC so it is always on.

What is the purpose of this 1k resistor?

Referencing typ app circuit on p1:

1. The 1k limits current when the input TVS clamps (either direction).
2. Along with COUT, allows for fast turn-off with input is shorted.
Is the reasoning regarding tying the MCU ground to VSS on LTC4359 valid?

Don't tie other references to the LTC4359's Vss pin.

Hope this helps,
-Aaron