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LTM4700 oscillates when paralleled

Category: Hardware
Product Number: LTM4700

We used two of your LTM4700 in parallel to supply up to 200A at 0,85V to an FPGA. However, a large oscillation (larger 100mV amplitude) emerges, when we use more than a single phase of the LTM4700.

When using all four phases available in the two LTM4700, we get an oscillation frequency of 17.8 kHz. When using only the two phases of the same LTM4700 (no matter which one), a 9.4kHz oscillation forms. The mean of this oscillation is exactly the desired 850mV output voltage. We assume it is some kind of instability, as it is nowhere near the switching frequency.

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We checked the design for stability in LTPowerCAD and also simulated in LTSpice, but there was no hint to the source of that oscillation. Unfortunately, we can not buy a multi-phase evaluation board due to the availability. We have connected the supplies as is demanded in the load sharing application in the datasheet (Figure 48) and stated on page 69/70.

We tried increasing the output capacitance by adding more capacitors, we tried different values for the internal Rth, but the oscillation persists.

Is this oscillating behavior known? Can you tell us a reason for that?

Thank you and best regards

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  • FormerMember
    0 FormerMember
on Oct 18, 2022 9:04 PM

Hi, 

Can you try increasing the capacitor between COMPB and SGND to say around 0.1uF and see if the oscillation still exists?

This method usually stabilizes the converter by slowing it way down. Although not 100% accurate, it can usually work if it is stability issue.

Regards,

Jhun

  • Hello Jhun,

    Thank you for your fast answer. Yesterday we tested your proposed method, with the result that the oscillation disappears, leaving only the (way smaller) switching noise.

    However from what we understood, this does slow down the regulation of the power module, so that the voltage swing from a changing load is greatly increased. This has also been verified using an LTPowerCAD simulation.

    We can only test the transient response of the system with some difficulties, so we currently rely on the simulation to show the full effect of your proposal.

    The question now is, what the final solution to our problem can be. Is it only about finding a sweet-spot between output stability and transient response or did our results hint to where the real problem is, why our module behaves so differently from the simulation and the datasheet's descriptions?

    Thank you in advance for your answer!

    Unfortunately, it is apparently not possible to embed pictures in answers anymore, so you need to use these links for oscilloscope picture and simulation results.

    Best regards,

    Torben

  • FormerMember
    0 FormerMember on Oct 23, 2022 10:23 PM in reply to tmehner

    Hi Torben,

    The best way to know is to measure the gain and phase margin. Generally acceptable gain margin is a minimum of 6dB and a minimum phase margin of 45deg.

    Is it only about finding a sweet-spot between output stability and transient response

    This is correct.

    The method that I have suggested is that to know if the instability is related to the loop compensation, not a permanent fix as it slows the loop way down.

    Regards,

    Jhun

  • Hello Jhun,

    Thank you for your answer!

    We are now only concerned why the simulation result is so far off the reality in our design. Do you have an idea on that?

    Best regards,

    Torben

  • FormerMember
    0 FormerMember on Nov 2, 2022 7:14 PM in reply to tmehner

    Hello,

    This might be because of the tolerances from both the device and external components. Keep in mind that the values are not ideal, and I think the LTPowerCAD is using the typical values.

    Regards,

    Jhun

  • Reply
    • FormerMember
      0 FormerMember
    on Nov 2, 2022 7:14 PM in reply to tmehner

    Hello,

    This might be because of the tolerances from both the device and external components. Keep in mind that the values are not ideal, and I think the LTPowerCAD is using the typical values.

    Regards,

    Jhun

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