LT3042
Recommended for New Designs
The LT3042 is a high performance low dropout linear regulator featuring LTC’s ultralow noise and ultrahigh PSRR architecture for powering noise sensitive...
Datasheet
LT3042 on Analog.com
LTspice
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LTspice® is a powerful, fast, and free SPICE simulator software, schematic capture and waveform viewer with enhancements and models for improving the simulation...
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Does the PG pin of the LT3042 sink current when the device is not powered (IN = EN = PGFB = GND = 0 V)?
The Absolute Maximum Ratings seem to allow this condition (maximum PG pin voltage is 22 V without regard to IN voltage).
The LT3042 model in LTspice suggests PG does not sink current until IN reaches about 1.22 V (maybe the Vgs threshold of the PG output transistor?) I am not sure if this behavior is modeled realistically in LTspice.
Motivation: I want to pull up PG and connect it to an N-MOSFET gate to turn on a relay (driven by a separate power rail). This rail can be high when the LT3042 supply is off. Thus if PG is high-impedance, the relay would wrongly close. (In this case I would need another transistor to break the relay circuit when IN is low.)
Thank you!
Hi dnintegrolution ,
Thank you very much for reaching out and for your participation in this community. I have contacted the ADI experts on this device to help respond to this query. We hope to give you an update as soon as possible. You can also try reaching out to local FAE to provide support on the product through this link: Technical Support Form | Analog Devices.
If you can give me your project information and estimated annual usage (EAU), I can help connect you to a local FAE. It may also be good to try and get hold of the demoboard as a reference board to easily debug your design.
Regards,
Noel
The LT3042 PG pin is not going to pull down until the LT3042 is enabled with VIN above its UVLO. I show a scope capture below for the LT3045, but the LT3042 will behave the same way. Also, I usually ask customers to only load PG to 100uA - 200uA which is similar to the condition of testing PG. I show the line item from the datasheet Electrical Characteristics table that has that condition in the other image below. In other words, your resistor that pulls up the gate of your FET will be so large that your FET will only turn on slowly and that may stress your FET.

Conditions: LT3045EDD, DC2491A, 5VIN, 3.3VOUT at 100mA, VCIN VEN VPG VOUT, EN startup_0.bmp PG is pulled up to VIN) PG IS MISLABELED OUT.

Hi Noel and ARad,
Thank you for your answer, this gives me the information I needed.
The project is an early stage prototype and it's unclear when it will enter production. Initial volume would be low: probably only 100 boards, each board using one LT3042 and one LT3093. I don't require any further support at this time but I thank you for the offer to check in with an FAE.
Just to follow up on a related behavior of the PG output, as it can be seen on the chart above, after the input voltage is applied while keeping EN low, according to the datasheet PG also should be low, but it isn't. This behavior should be either noted on the datasheet or an errata should be issued. In our application Rpg is connected to the voltage feeding the logic, so we can see the exact same voltage levels as in the chart.
