During my design stage I encountered some issue/question:
Let suppose that Vcontrol is on (for example 7V), SET has resistor of 330K for 3.3V output.
Vin is 5V.
There is no sequencing requirement in the datasheet, so I have a scenario where Vin is only start rising after Vcontrol is on. (like on/off switching with Vin and not Vcontrol).
In this case the Vcontrol will place the 10uA to the SET resistor and SET voltage will be 3.3V, BUT the output is still 0V or rising since Vin is not fully up yet.
This violates the absolute maximum rating requirement for the SET pin which is +-0.3V for VOUT.
- How is this possible? I saw there is a clamping diode from out to set so maybe it will work in this state (which direction is the clamping diode?). Maybe is it +-0.3V when Vset is externally being sourced like DAC/OPAMP output (meaning I can source higher currents to it, and destroy the internal clamping diodes(note 7) from SET to VOUT), but not when using the simple RSET resistor and the current is limited to 10uA?
- The LT3083 is very similar to LT3080 but there the limit is +-10V. why the difference?
- I ask those questions because I saw in simulation that toggling Vcontrol for ON/OFF (when VIN is fully on) cause the output to have some momentary "glitch/spike", but those glitches/spikes don’t exist if I am toggling VIN (while Vcontrol is fully on). but i dont want to violate SET rating vs out when toggling VIN (using fet on set pin is not good for me since i cant add extra accuracy error to the output)