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LTC4366-2 MOSFET Gate Charge and ESR

Category: Software
Product Number: LTC4366-2


I've been working on a circuit that uses the LTC4366-2 as a surge and spike protection circuit. I designed the circuit simulation in the LTSpice with LTC4366-2. I have applied spike test within the ranges specified below. 


I have used different MOSFET than simulation. Product number of MOSFET that I used is IPDQ60R010S7AXTMA1 in my application. The mosfet have 318nC total gate charge. I choosed  value of total gate charge close to my MOSFET from LTSpice Library.

Also I have used two 120uF capacitor  that ESR value is 1.47 ohm in source of MOSFET.  


When I have run simulation, I saw 238V spike during 11us  in simulation result and the design didn't make clamping straight. The simulation picture is below. 

I think,

1) Could it be a problem, due to total gate charge of my mosfet ? If it is problem, How I can handle gate the problem with this mosfet?

2) Is important ESR value of capacitor for spike seen in output?  

I shared circuit picture and LTSpice simulation file at the attachment.

The Circuit Sİmulation 0081.Draft1.asc

gramer changes
[edited by: Baran at 10:52 PM (GMT -4) on 29 May 2022]
  • Hi Baran,

    The input surge is so fast. Can you try to slow it down while checking what is surge specs of system that you want to put this solution into? I also will recommend that you try this in bench after making it work in LTspice. I don't think ESR value of output capacitors matters on the spike seen. I believe it is more about the capability of the IC to drive the FET properly so more about choice of FET and the spike at the input.