LTC3225, LTC4412, Supercapacitors Can Replace a Backup Battery for Power Ride-Through Applications − Design Note 450

Info:
With the first approach I used, I had only 220mF and they had a very worse ESR of 40 Ohm! (2x 220mF in Series, with CX in middle, schematic^^)
(Sorry, I forgot to mention that I also used an other value than in the Application Note, because I didn't had this capacitor then.)
So I guess the oscillation at PGOOD is because of this high ESR and the fast voltage drop because of the too small capacitance.

Update: 
When changing the supercaps to 2F/3V and only 100mOhm ESR the result was much better.
Now the voltage drop is less and the discharging curve looks as expected.
(I have still around 4 Volt after 2.5 s)

However, I can still see that the FET's have loss in the path when switching to the backup voltage of the supercaps (so they are not fully conductive respectively blocking).

Update2: 

I changed the FET's, now it's looking much more digitally

Instead of the P-FETs NTLUD3A50PZTAG I use now the FETs Si9953DY (which I had available, but are obsolete).

It works now properly :)

But now my Question is, why does it work with the one FET's but not with the other (similar specs)?

Which parameter for the FETs are important?

Irina - did you ever get to the bottom of this ? I am looking at the same issue know - but with an SI2301CDS - rather than an SI9953 -- and cannot quite work out what the key spec/param is that is wrong. 

Hi Dirkx

I came to the conclusion that my originally assumption with the power losses (when it's not digitally) is wrong.
When I just look at the output (VCC_5V0_PANIC) it has similar behavior as described in the application note.
And at the end the 'non-digitally'-mode performed better (longer delivery of voltage, because the decreasing curve was less steep).

Here's why a non-digitally-mode is preferred:
The LTC4412 tries to regulate the voltage drop across the MOSFET to 20mV (it is kind of a control loop). 
So, when the Rdson of the FET is better (smaller), it results in this 'non-digitally'-mode (because the FET's don't have to be fully conductive to reach this voltage). On the other hand, when using an older and typically worse FET with bigger Rdson value, than the FET's must be fully conductive to try reaching this 20mV. If it can't reach this 20mV even when the FET's are fully conductive, this leads to a reduced performance due to the higher path losses.


At the end i used following components and it seems to work properly:

Supercap: SCCQ12E105PRB (C=1F, 3V (-40...+65 deg), ESR (@1kHz): 0.240 Ohm, ESR (DC): 1.5 Ohm)
FETs: FETUT6JB5 or NTLUD3A50PZTAG (should be better)

Hi Dirkx

I came to the conclusion that my originally assumption with the power losses (when it's not digitally) is wrong.
When I just look at the output (VCC_5V0_PANIC) it has similar behavior as described in the application note.
And at the end the 'non-digitally'-mode performed better (longer delivery of voltage, because the decreasing curve was less steep).

Here's why a non-digitally-mode is preferred:
The LTC4412 tries to regulate the voltage drop across the MOSFET to 20mV (it is kind of a control loop). 
So, when the Rdson of the FET is better (smaller), it results in this 'non-digitally'-mode (because the FET's don't have to be fully conductive to reach this voltage). On the other hand, when using an older and typically worse FET with bigger Rdson value, than the FET's must be fully conductive to try reaching this 20mV. If it can't reach this 20mV even when the FET's are fully conductive, this leads to a reduced performance due to the higher path losses.


At the end i used following components and it seems to work properly:

Supercap: SCCQ12E105PRB (C=1F, 3V (-40...+65 deg), ESR (@1kHz): 0.240 Ohm, ESR (DC): 1.5 Ohm)
FETs: FETUT6JB5 or NTLUD3A50PZTAG (should be better)