LTC3300 SPI mode not consistent

I did additional tests by inserting a delay between CS down and start of the clock, adding a dummy clock beat between the read command and the start of reading data sent by the LTC3300, and at different clock rate.  Always the same result:  the data bits out of the LTC3300 are shifted 140ns after the rising edge of the clock (when it should be within 250ns after the falling edge). 

Can anyone at Analog Device help me find the cause for this problem?

More details:

I did the same tests using the old MCU PCB (ATmega2560)... and found that the traces are exactly the same - meaning that when the LTC3300 sends data bits, they are shifted on the rising edge of the clock - so it is consistent and the issue is not new.

I guess I was lucky that the old MCU could read the data sent by the LTC3300 - although it was unstable and I had to read in a loop until I could get the correct CRC (at the time I thought it had to do with the PCB design and I did not worry considering I could get a good reading with 10 loops). 

I am not that lucky now with the ESP32-s2 and readings are always wrong!! 

Hello,

I was just looking at this. What I can see on the scope shots it appears that the LTC3300 might be sampling on the rising edge and shifting out on the falling edge. I am thinking that it might not be SPI mode 3. I would expect mode 2. Is it possible to see if changing modes fixes the problem?

Hi Marty,

Thanks for your suggestion.  Here are the traces using SPI mode 2:

It shows that the LTC3300 does not register the write command as the read back returns 0's.

That confirms LTC3300 expects SPI mode 3 when writing to it, but it uses SPI mode 2 when sending data (reading from it).

I think Analog Device is confused about SPI mode.  The descriptions of the modes on the AD document you attach are wrong (CPOL and CPHA are right, but the descriptions are swapped between mode 2 and mode 3).

 Here are a few way it is described by others:

"With inverted clock polarity (i.e., the clock is at logic high when slave select transitions to logic low):

• Mode 2: Clock phase is configured such that data is sampled on the falling edge of the clock pulse and shifted out on the rising edge of the clock pulse.
• Mode 3: Clock phase is configured such that data is sampled on the rising edge of the clock pulse and shifted out on the falling edge of the clock pulse." 

or:

and:

They all say the same thing and it is different from what Analog Device says in this article published on its official website:  https://www.analog.com/en/analog-dialogue/articles/introduction-to-spi-interface.html - this is worrying!

Based on these definitions and the LTC3300 datasheet, the LTC3300 uses SPI mode 3 (CPOL=1, CPHA=1):

Please tell me that I am wrong and tell me what needs to be done for the LTC3300 to behave the way it is detailed on the datasheet.

Let me know if you need more tests and measures.

This issue has still not been addressed properly or resolved.

I have been in contact with the Australian Field Application Engineer who confirms that there is a discrepancy between what is observed and the datasheet.  He was going to refer that matter to ADI experts but still no reply after many months and no more answers from the FAE!

As ADI has been unresponsive and all our measures show that the LTC3300 does not comply with the datasheet, we are now thinking about redesgning our balancing PCB without the LTC3300 - which we would prefer not to do! 

Can someone from ADI get back to me so that we can get that issue sorted out.  
PLEASE HELP