LDC - UVLO Frequency Limitation

Hi Roy,
A schematic (or block diagram) and scopeshot would be useful.

If I understand correctly:
Two series 12V supplies, with 1 being enabled/disabled at 5kHz (12V > 24V >12V, etc)
While V_IN enters and exits the UV-OV window at 5kHz, you expect to see V_OUT with the same 5kHz signal

There is a 36ms recovery delay waiting period (t_RECOVERY) following a UV-OV fault.
That's a frequency of ~28Hz, which is close to what you are seeing.

-Aaron

Hi Aaron,

That should be it, thank you. Does AD has any similar UVLO IC to switch under a much higher frequency? I've found one with 1ms t_recovery, but that's still only 1KHz. 

Best wishes,

Roy 

Hi Aaron,

I never used LT spice before, so I haven't built my circuit on that. I'll try the RC circuit. The foot print of LTC4365 is really small, it's kind of hard to change the circuit for testing. I'll look into LTspice as well.

Best wishes,

Roy 

Hi Aaron,

I used LT Spice to simulate my design and the UVLO result seems promising, therefore I redesigned my PCB and have it test without load in the workshop today. The circuit still cannot perform as simulation goes. My input has 24.06vdc and output nothing. FAULT pin returns 0 vdc, SHDN returns 21.87vdc, GATE 0vdc. Here's the LT spice schematic file for simulation and design. My scope is not working today and trying to fix it, let me know if you need scope shots. Much appreciate.

Best wishes,

Roy3107.4365_test.asc

Roy,
Your simulation is different from the schematic you sent me:
1. Different UV-OV resistor values
2. Different R_LOAD
3. Different C_LOAD

I made some minor mods to your sim:
1. Each FET gets a 10Ω resistor
2. Input steps to nominal 24V

Simulation shows 32A of inrush current.

Do you really have 1mF of output capacitance?
If so, you need to add inrush control so the FET's safe operating area is not violated (see page 14 in datasheet).

A scopeshot of startup would be useful:
1. Step input from 0V to 24V
2. Probe IN, OUT, GATE, and CURRENT
3. If you don't have a current probe, measure FAULT# (fault needs a pull-up, can't be floating)

8765.4365 EZ 4-12-22.asc

-Aaron

Hi Aaron,

I did some changes according to your advice. And I change the UV to 20.5Vdc, OV TO 26Vdc for wider operational window. Could you take a look at the simulation before I go and order PCB? I was kind of worried about the I_Gate here. If the simulation and numbers are promising, then I'll move on and order PCB for testing in real life.

Best wishes,

Roy

4365Test_2.asc

Roy,
With your new UV-OV resistor values, the thresholds are now:

UV_RISE = 23.301
UV_FALL = 22.181
OV_RISE = 27.312
OV_FALL = 25.947

If you are adjusting resistor values by sweeping V_IN and seeing when GATE and V_OUT goes high, you must sweep V_IN very slowly, to account for GATE recovery delay time (t_RECOVERY).

Running your sim:

V_DS ramps from 0V to 24V in 2.3ms.
We can say this is a constant 12V for 2.3ms (for easy SOA calculation).

Current ramps from 0A to 5.4A during this time.
We can say this is a constant 2.7A (for easy SOA calculation).

Plot these points on the Safe Operating Area (SOA) graph of the SQ4282EY FET from your schematic:

12V_DS , 2.7A is approximately on the 10ms curve.
2.3ms < 10ms, so you should be fine.

Once you settle on an OV_RISE, repeat these steps for OV_RISE applied to input, as it is the most stressful scenario. I think you have enough margin in the typical 24V case to pass though.

-Aaron

Hi Aaron,

I'm not too worried about OV situation since the PSU I used could only offer 24vdc. But the measurement I did looks good and within the SOA. However, LTC4365-1's GATE pin current when shutting the circuit down has a maximum around 50 mA. Is it going to be an issue? 

Best wishes,

Roy

Roy,
That's I_GATE(FAST) , to quickly turn off the FETs during UV or OV faults.
Not an issue.

-Aaron

Thank you so much Aaron. Have a good one.

Best wishes,

Roy

Hi Aaron,

I've been doing a new UVLO design using LTC4367-1. The proposed parameters are following:

UV=27.5V, OV=60V,

Nominal input voltage=48V

Dual N-Channel MOSFET: BSO604NS2

And the LTSpice simulation file is attached.

The issue is, the simulation looks fine, but after I built the circuit and test it, it let 24v pass through and 48v blocked. FAULT Pin is pulled low under 48v input, about 24mv. Could you please check the circuit simulation and give me some advice on that?

Best wishes,

Roy

4367-1 Simulation.asc

Hi Roy,
In your simulation, you assigned the following resistor values in your UV-OV divider:
RTOP = 16.2Meg
RMID =162.5k
RBOT = 137.5k

Mathematically, you should get:
UVRISE = 28.875
UVFALL = 27.5
OVRISE = 60
OVFALL = 57

Your simulation is in sync with these values.
The thing that stood out to me was the size of the resistor values.
They're huge!
As a rule of thumb, try to keep resistor values <1Meg.
Flux from your solder joints provides a leakage path around your large resistor.
The larger your resistor values are, the more this leakage path influences the equivalent resistance.

Try using these standard 1% values instead:
RTOP = 590k
RMID = 5.90k
RBOT = 4.99k

They should get you the same UV-OV thresholds.

-Aaron

Hi Roy,
In your simulation, you assigned the following resistor values in your UV-OV divider:
RTOP = 16.2Meg
RMID =162.5k
RBOT = 137.5k

Mathematically, you should get:
UVRISE = 28.875
UVFALL = 27.5
OVRISE = 60
OVFALL = 57

Your simulation is in sync with these values.
The thing that stood out to me was the size of the resistor values.
They're huge!
As a rule of thumb, try to keep resistor values <1Meg.
Flux from your solder joints provides a leakage path around your large resistor.
The larger your resistor values are, the more this leakage path influences the equivalent resistance.

Try using these standard 1% values instead:
RTOP = 590k
RMID = 5.90k
RBOT = 4.99k

They should get you the same UV-OV thresholds.

-Aaron

Hi Aaron,

Thank you for your advice! I'll give it a go.

Best wishes,

Roy