LDC - UVLO Frequency Limitation

Hi Roy,
A schematic (or block diagram) and scopeshot would be useful.

If I understand correctly:
Two series 12V supplies, with 1 being enabled/disabled at 5kHz (12V > 24V >12V, etc)
While V_IN enters and exits the UV-OV window at 5kHz, you expect to see V_OUT with the same 5kHz signal

There is a 36ms recovery delay waiting period (t_RECOVERY) following a UV-OV fault.
That's a frequency of ~28Hz, which is close to what you are seeing.

-Aaron

Hi Aaron,

That should be it, thank you. Does AD has any similar UVLO IC to switch under a much higher frequency? I've found one with 1ms t_recovery, but that's still only 1KHz. 

Best wishes,

Roy 

Roy,
The parts that I support (LTC4365/7/8) have at least a 500us t_RECOVERY.

These parts were designed for DC applications. The recovery timeout period was put in to filter out line noise and prevent the load from chattering.

Have a good day,
-Aaron

Roy,
The parts that I support (LTC4365/7/8) have at least a 500us t_RECOVERY.

These parts were designed for DC applications. The recovery timeout period was put in to filter out line noise and prevent the load from chattering.

Have a good day,
-Aaron

Hi Aaron,

Thank you for your advice. I'll look into it. I'll let you know if I run into more issues. Have a nice one.

Best wishes,

Roy

Hi Aaron,

I am running into another issue. I removed the PWM load and use several resistors as load. Therefore the output should not have any frequency issues. But the LTC4365 still cut the output off. I'm using a series of resistor to get 6.8 ohms under 24v, which is created by series 2 12vdc POE power supplies. But once I connected the load to it, it get a pulse of  0.85 A maximum and then shut down within micro seconds. What's the issue here? Please see the attached file for oscilloscope plot.

Best wishes,

Roy

Roy,
Please attach a schematic of the circuit.
What FETs are you using?
What is your nominal load current?

Does the GATE and OUT come up with no load?
Let's see a scopeshot of turn-on while looking at these pins:
P1: IN
P2: OUT
P3: GATE
P4: FAULT#

Btw, 24V with 6.8Ohm means the load has to dissipate 85W!
Are you ready for that?

-Aaron

Hi Aaron,

Please see the attached file for schematic and scopeshots.

I'm using a DUAL N-CHANNEL MOSFET, Prt No. SQ4282EY-T1_BE3.

Nominal load current should be 4.98A (Ideally).

Yes the GATE and OUT come up correctly with no load.

I was wrong about the R_ equivalent, it should be 4.82Ohms, and they gonna dissipate 119.5W. The reason why for this is that I'm testing the POE++ power supply, where single power supply could offer 85 to 90W maximum. To make sure those two power supply is working together I need to get 119.5W out of them. And I'm using resistors that could handle that amount of energy. The details can be found in the schematic. 

Best wishes,

RoyUVLO Testing.zip

Roy,
I see a couple things:

1. No gate resistors. Could result in FET self oscillation. Place series 10Ω resistors as close as you can to the gate of the FETs.
2. No inrush control. I don't see any load capacitor, but an RC on the gate pin would control the amount of inrush into a gate. If nothing else, a gate RC will allow you to control the slew rate of the output for a softer start.

Have you tried building your circuit in LTspice for a sanity check?

-Aaron

Hi Aaron,

I never used LT spice before, so I haven't built my circuit on that. I'll try the RC circuit. The foot print of LTC4365 is really small, it's kind of hard to change the circuit for testing. I'll look into LTspice as well.

Best wishes,

Roy 

Hi Aaron,

I used LT Spice to simulate my design and the UVLO result seems promising, therefore I redesigned my PCB and have it test without load in the workshop today. The circuit still cannot perform as simulation goes. My input has 24.06vdc and output nothing. FAULT pin returns 0 vdc, SHDN returns 21.87vdc, GATE 0vdc. Here's the LT spice schematic file for simulation and design. My scope is not working today and trying to fix it, let me know if you need scope shots. Much appreciate.

Best wishes,

Roy3107.4365_test.asc

Roy,
Your simulation is different from the schematic you sent me:
1. Different UV-OV resistor values
2. Different R_LOAD
3. Different C_LOAD

I made some minor mods to your sim:
1. Each FET gets a 10Ω resistor
2. Input steps to nominal 24V

Simulation shows 32A of inrush current.

Do you really have 1mF of output capacitance?
If so, you need to add inrush control so the FET's safe operating area is not violated (see page 14 in datasheet).

A scopeshot of startup would be useful:
1. Step input from 0V to 24V
2. Probe IN, OUT, GATE, and CURRENT
3. If you don't have a current probe, measure FAULT# (fault needs a pull-up, can't be floating)

8765.4365 EZ 4-12-22.asc

-Aaron

Hi Aaron,

I did some changes according to your advice. And I change the UV to 20.5Vdc, OV TO 26Vdc for wider operational window. Could you take a look at the simulation before I go and order PCB? I was kind of worried about the I_Gate here. If the simulation and numbers are promising, then I'll move on and order PCB for testing in real life.

Best wishes,

Roy

4365Test_2.asc

Roy,
With your new UV-OV resistor values, the thresholds are now:

UV_RISE = 23.301
UV_FALL = 22.181
OV_RISE = 27.312
OV_FALL = 25.947

If you are adjusting resistor values by sweeping V_IN and seeing when GATE and V_OUT goes high, you must sweep V_IN very slowly, to account for GATE recovery delay time (t_RECOVERY).

Running your sim:

V_DS ramps from 0V to 24V in 2.3ms.
We can say this is a constant 12V for 2.3ms (for easy SOA calculation).

Current ramps from 0A to 5.4A during this time.
We can say this is a constant 2.7A (for easy SOA calculation).

Plot these points on the Safe Operating Area (SOA) graph of the SQ4282EY FET from your schematic:

12V_DS , 2.7A is approximately on the 10ms curve.
2.3ms < 10ms, so you should be fine.

Once you settle on an OV_RISE, repeat these steps for OV_RISE applied to input, as it is the most stressful scenario. I think you have enough margin in the typical 24V case to pass though.

-Aaron