Managing Output Voltage ADP1764 LDO with LTC2977

Hi bobKof,

The 1764 has a 50uA current source that develops a voltage by connecting a resistor from VADJ to GND.  I would like to refer you to the DC2518 demo board.  On this board I used an LT3081 which has a similar arrangement with the SET pin.  It's a little diferent since the 1764 provides 3x voltage gain from VADJ to VOUT.  However the concept is similar.  If you go to page 16 of the DC2518 demo manual, you will see the SET resistor is split into 2 resistors and the midpoint to tied to the 2977 DAC.  In the 1764 case, you may not need to have 2 series resistors.  You could tie a DAC resistor from the 2977 DAC pin to the VADJ pin. The key to making this work is that the VADJ pin must be at least 200mV above GND for the 2977's DAC to properly soft-connect to the VADJ node at startup.

https://www.analog.com/media/en/technical-documentation/user-guides/dc2518afa.pdf

I've run a few LTspice sims and depending on how much margin range you need, the resistor values can be changed to suit your needs.  You ought to select a VADJ resistor such that it determines the nominal Vout voltage.  Then the DAC resistor can be selected to the margin range.

Mike 

Hi Mike,

Thank you for the fast response. However, I'm not sure I fully understand your solution.

The nominal output voltage of the 1764 is 0.75V and the margin is +/-15%. So, the VADJ should be 0.25V +/- 15%.

In case of using 1 resistor or 2 resistors the LTC2977 VDAC is limited to 0-0.2V, thus the resolution is degraded.

How can use the DAC full scale of 1.38V to output 0.75 +/-15%?

Note: I've simulate the 1764 using LTspice and using a resistor divider for the DAC is not working well.

Regards,

Itay

Hi Itay, 

Thanks for providing your specs.  To margin Vout +/-15% of 0.75V, the ADJ pin needs to go from 200mV to 300mV.  With the 2 resistors, you are correct that only a portion of the DAC range will be used.  To map the 1.38V DAC range to the 200 to 300mV ADJ range, we need to devise a translator circuit.  Attached is a first attempt at a circuit.

A PNP collector is tied to ADJ and the PNP emitter is tied thru a resistor to the 2977's VDD33.  The collector current is summed with the 1764's 50uA current. When the DAC is hi-Z, you need the ADJ resistor value to be 250mV/(50uA+15uA) = 3.84k (3.83k is 1% value). I chose a PNP pre-bias current of 15uA to provide headroom.  To margin low, PNP collector is close to zero and to margin high, PNP collector current is ~30uA.  The emitter resistor is split into R5/R6 to increase the midpoint of the DAC range.  This arrangement maximizes the DAC range.

Mike