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ADM1270 FET gate details and misc

Some details I can't seem to find out about the ADM1270.

Is the P fet driven linearly or not?  Its not super clear in the datasheet how current limiting is accomplished.

What should be done with the RPFG pin if not used?

Also, am I missing something, or why is the SOA plot in the design tool hard coded?

  • Hi Erik,

        The PFET is driven such that current is maintained below the ISET current limit. If current remains below the limit then the PFET Vgs is maintained in the fully enhanced region, near Vgs=-12V. If current reaches the ISET limit the PFET Vgs voltage goes down to near the FET Vth (linear region), thus controlling the current.

        The RPFG pin can be left floating if it is not used.

        The SOA plot in the tool is an example. You can past your own screen grab of any FET you like. The idea is to pick off the numbers from your desired SOA diagram and plug those numbers into the calculator.



  • Do you mind reviewing these specs?  My target is 3A max for nominal 1.25A @ 24V with up to 5000uf capacitance.

    NTB25P06T4G mosfet

    0.010R sense resistor

    UV 12V

    OV 26V

    FLB threshold 10V

    On Timer 100ms

    In my opinion it is a bit tricky to calculate a good timer value with either the spreadsheet or ltspice.  I did some experiments with a modified dev board and quickly found how important this foldback calculation is due to the low voltage foldback.  Either a ltspice model or some extra calculations on the excel "Start up time" calculations would be quite helpful here.  The standard calculation does not factor in the foldback limits.