fold back assistance ADM1270ACPZ-R7

Hi Clancy,

    As VOUT rises Vds falls, and you want to select a point on the SOA diagram where you are satisfied that the FET can take the full Vds for the time allowd by the TIMER capacitor. During fully enhanced operation the current is limited to ISET, but when VOUT is below a level of your choosing (when  Vds is large enough to cause the FET to self-heat excessively) you want less current, so design the FLB resistor divider such that V(FLB) = V(ISET)/2 at that point.

    For your particular FET, the SQS415ENW, operating at 4A (at room temperature) and with a TIMER capacitor of 100nF (= 10ms) you don't want more than about 1.5V across the FET.This is actually not much. You may need a better FET with more SOA.

    The trick for you is that VIN has the wide range of 9V - 30V. If you want to protect the FET when VIN = 9V you need a resistor divider such that V(FLB) = V(ISET)/2 when VOUT= 7.5V. But when VIN=30V you want a different resistor divider to set the equality when VOUT=30V-1.5V=24.5V. Significantly different requirements. Again, a better FET would make this job easier.

    If you have not already done so, I recommend that you take a look at the schematic for the EVAL board for the ADM1270. It shows a working example that you can use to reality check your design.

Thanks!

  Nathan

Hi Clancy,

    As VOUT rises Vds falls, and you want to select a point on the SOA diagram where you are satisfied that the FET can take the full Vds for the time allowd by the TIMER capacitor. During fully enhanced operation the current is limited to ISET, but when VOUT is below a level of your choosing (when  Vds is large enough to cause the FET to self-heat excessively) you want less current, so design the FLB resistor divider such that V(FLB) = V(ISET)/2 at that point.

    For your particular FET, the SQS415ENW, operating at 4A (at room temperature) and with a TIMER capacitor of 100nF (= 10ms) you don't want more than about 1.5V across the FET.This is actually not much. You may need a better FET with more SOA.

    The trick for you is that VIN has the wide range of 9V - 30V. If you want to protect the FET when VIN = 9V you need a resistor divider such that V(FLB) = V(ISET)/2 when VOUT= 7.5V. But when VIN=30V you want a different resistor divider to set the equality when VOUT=30V-1.5V=24.5V. Significantly different requirements. Again, a better FET would make this job easier.

    If you have not already done so, I recommend that you take a look at the schematic for the EVAL board for the ADM1270. It shows a working example that you can use to reality check your design.

Thanks!

  Nathan

thankyou for your response.