The scheme is developed according to the datasheet. Nominal input voltage is 24V, output - 12V, 2A
The PCB is designed carefully with minimum trace distances, current loops, taking into account the recommendations from the datasheet.
Digital PWM control from 3.3V MCU was translate to ~2V level to CTRL & PWM inputs.
So the circuit works properly as long as we don't use the EN/UVLO signal. If closing and next opening the Q1 transistor or UVLO function enabling the device when PWM & CTRL signals have active state, then the LT3932 chip is permanently damaged. Several chips burned out before I determined the dependency. The presence of the load does not affect the result.
The only way to get around this issue is don't use the EN/UVLO fuction, and use an external UVLO circuit with a trigger voltage higher than calculated for the LT3932. The fault signal from external UVLO circuit must be applied to MCU reset, power monitor or NMI to disable CTRL and PWM levels in power transient states.
Updated schematic with VOUT connection
[edited by: German_K at 8:19 PM (GMT -5) on 9 Jan 2022]
