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ADM1272 I2C/SMBUS interface



		

			

									
						ChesterChen
					
							

			
				
									
											
							 		
		        	            							
			
			    	
			                    
                
				                on Dec 29, 2021 
				
			
			
		


				
		

		    		    
		    
		    	
			
Hi Expert




Since ADM1272 have the power cycle function. And I have found OC fault,CML,nonebove when doing power cycle.


So I would like to have a question about this.


Does ADI has any suggestion about how long the system needs to be turned on and ready to read/write the ADM1272?


thank you in advance and looking forward to receiving your feedback. thanks




PS. power cycle testing are made by pin6 ENABLE. and it will see alert when quickly switch ENABLE.

										


				add description for power cycle test by ENABLE 

[edited by: ChesterChen at 5:45 AM (GMT -5) on 30 Dec 2021]
				

					


				
				
		

			
						
									
									
						
						
			
			
			
			
		


					

			





	










	

	

					



			


				
	









	
    
	

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													+1
							
			
				
									
							        
            
                                                                                    
      
                            
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                                 Analog Employees 
                                
                            
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                on Jan 3, 2022 7:04 PM
            
            
					
    
	
    

		
		
    
					
    Hi Chester,
    

        You seem to be talking about two different functions of the ADM1272. The POWER_CYCLE PMBus command (0xD9) causes the ADM1272 to turn off the FET for a programmed amount of time (default is 10.1sec in the RESTART_TIME reg (0xCC)). The ENABLE pin of the IC enables and disables the FET asynchronously. Since you mention pin6 I assume that you are not using the PMBus command.
    

        When you toggle the ENABLE pin quickly off and on the output does not have time to drop, and therefore the load may remain energized when ENABLE goes high again. If the load is still drawing current then the ADM1272 may hit the ISTART current limit and trigger an OC fault.
    

        The most likely cause of CML fault is a disruption of the I2C bus during the power cycle. If the I2C bus has glitches during a transaction then the ADM1272 may receive partial transactions and detect a communication fault. It should be straightforward to probe the I2C bus, either with a scope or with a Beagle, to detect these partial transactions.
    

        If during the testing the ADM1272 VDD remains high then the IC should remain active and it should communicate correctly on the I2C bus as long as there are no bus errors. There is no ADM1272-specific requirement for waiting after a power cycle. The requirement is that the bus remain clean.
    

    Thanks!
    

      Nathan
    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
						
						
				
				
		
		
    
			
		
    
	
    

    

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													+1
							
			
				
									
							        
            
                                    			
			                            
                        
                on Jan 6, 2022 2:25 AM
            
            
												
						in reply to nenger
					
									
    
	
    

		
		
    
					
    Hi Nathan
    

    

    Many thanks for your reply.
    

    it seems that is caused by ISTART & ISET.
    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
				
						
						
				
				
		
		
    
			
		
    
	
    

    

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