LT3743 Current Rising Problem (at Strobe drive, 20A)

Hi Namuree,

Do you set the PWM pin high and low to control the output current level? What is the PWM on, off time? 

Can you please try to keep Cboot at 220nF and add a 1k resistor in parallel with Cboot to see if it works normally?

Thanks, 

Peter Pham

Thank you very much for your comment.  Sorry for late.

I did as you suggested.

1kOhm Parallel with Cboot.

Oh~~~! So Good!   Changed to normal.

Before 

After   

The above signal PWM is always high.
Instead, set the current value to the Ctrl_H terminal.
Of course, after it is installed in the equipment, high and low signals are input to the PWM terminal and the result is the same.

As your suggestion in my last question fixed the problem by connecting a 1kOhm resistor in parallel to the 220nF Capacitor.
I really appreciate the reply.
I'd love to hear a more detailed explanation of how this happens.
Customers have concerns that it may occur in the future, so countermeasures are necessary.
I wonder why it is 1kOhm and what effect it has when driving a FET.
There were only a few FETs in the lot that caused the problem, and the FETs in the other lot didn't cause any problems at all.
The bad FET was sent to RENESAS for inspection, but got a reply saying there was no problem.
It would be very much appreciated if you could tell us the detailed operation and effect of CBOOT, C3, and R26.
I hope you are always healthy and full of happiness.
Thank you.

There is a mechanism inside the IC that prevents the Cboot-SW voltage from dropping too low. When the Cboot-SW voltage is decreased down to around 2V, the IC turns on the low-side FET to pull down the sw node to GND in order to charge Cboot for a short time, then turns off the low-side FET. 

For example, I added a 1k resistor in parallel with Cboot in the LTspice model below. During the off-time of the PWM (enable) signal, both switches are off leaving the sw floating. During this time, the parallel resistor discharges Cboot until Vcboot-sw drops to 2V. Then you can notice a voltage spike on the LG signal turning on the low-side switch. That allows Cboot to be charged and increases the cap voltage to a higher value. This is the "Boot-Refresh" event.

This protection ensures Cboot has enough charges to fully turn on the high-side FET (operating in the ohmic region) during the next on-time of the PWM (enable) signal. When operating a MOSFET as a switch, you want it to be in the ohmic region, not the saturation because Rds,on is lower in the ohmic region. 

For your old circuit without the parallel resistor, I think during the off-time of the PWM (enable) signal, the Cboot-SW voltage drops too low for some reasons, but not below the 2V threshold. That means the Boot-Refresh event is not triggered and there are not enough charges to turn on the high-side FET in the next PWM signal on-time. The voltage drop on Cboot could be caused by the leakage current from the diode.

By adding the resistor in parallel with Cboot, the cap is discharged faster so that the Boot-Refresh event is triggered and charges the cap as shown in the figure below.