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ADP5070 has no negative voltage

Hello,

here is my design to have a look at. It was taken from an app note 1:1. Little diff. for the Output voltages, but no Focus here. I do not get any negative voltage out of this device. The upper Regulator works best! Changing R9 and/or R11 and/or R10 does NOTHING. I do not get any VREF (1.6V) out of that chip. Changed the ADP 2 times - no result. Play around with values for COMP2 and L4 (up to 15µH has again no result. Play around with CR3 - no voltage on Output anyway.

Did mesurements on pcb, no Errors to discover...

Need direct Support from an ad engineer to sent complete files (include pcb-data)!

What is the Problem here?

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  • Hello Fil,

    did the needed changes. No luck. This design was taken from the app-note AN-1359 (below their data sheet) dealing with this filter network around my R11, but without the coil. The capacitors are well chosen. When I put manually -9V (or more than -5V) to the C16, the next stage will perform -5.0V with the not seen ADP7182ACPZN-5.0R7. I need +5.0V and -5.0V as good as possible for an TIA with pre- and post amp for an optical receiver. That's why I make here a big bang for it. I just wondering why I do not get any VREF. So there is nothing to measure... I removed R9 now, and C12 is now only 1µF/16V good capacitor - but no voltage on this output. As far as I understand, this 1.6V should come out of the VREG 4µA SS-port via the start-up timers in direction to the reference generator which has 3 outputs (page 14) these outputs are REF1, REF2 and REF_1V6. Ideas? Why are no voltage made here? Layout has no issues, no short circuit or something else. It seems that the lower inverter will not work either... Cheers, Thomas 

  • Hi Thomas,

    R9 is necessary and should not be removed. I was referring to R11. R11 is used as filter in the app note.

    I am not surprised why you don't see VREF. It is because you don't have output and therefore VFB. VREF is kind of unique in this design in that it is sort of derived from VFB. If no VFB, then no VREF.

    I was going to say layout. Good to know it has no issue. Make sure you get the demo board as reference layout design. I can send PCB gerber file if necessary.

    Please get the requested waveforms so I can help you better in the analysis. You may send files to fil.balat@analog.com

    I will move this thread to Power by Linear.

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  • Hi Thomas,

    R9 is necessary and should not be removed. I was referring to R11. R11 is used as filter in the app note.

    I am not surprised why you don't see VREF. It is because you don't have output and therefore VFB. VREF is kind of unique in this design in that it is sort of derived from VFB. If no VFB, then no VREF.

    I was going to say layout. Good to know it has no issue. Make sure you get the demo board as reference layout design. I can send PCB gerber file if necessary.

    Please get the requested waveforms so I can help you better in the analysis. You may send files to fil.balat@analog.com

    I will move this thread to Power by Linear.

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